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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dti,j721e-pci-host.yaml66 const: 0x104c
70 - 0xb00d
71 - 0xb00f
72 - 0xb010
73 - 0xb013
129 reg = <0x00 0x02900000 0x00 0x1000>,
130 <0x00 0x02907000 0x00 0x400>,
131 <0x00 0x0d000000 0x00 0x00800000>,
132 <0x00 0x10000000 0x00 0x00001000>;
134 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
[all …]
/openbmc/linux/include/linux/comedi/
H A Dcomedi_pci.h19 #define PCI_VENDOR_ID_KOLTER 0x1001
20 #define PCI_VENDOR_ID_ICP 0x104c
21 #define PCI_VENDOR_ID_DT 0x1116
22 #define PCI_VENDOR_ID_IOTECH 0x1616
23 #define PCI_VENDOR_ID_CONTEC 0x1221
24 #define PCI_VENDOR_ID_RTD 0x1435
25 #define PCI_VENDOR_ID_HUMUSOFT 0x186c
/openbmc/linux/Documentation/PCI/endpoint/function/binding/
H A Dpci-test.rst12 vendorid should be 0x104c
13 deviceid should be 0xb500 for DRA74x and 0xb501 for DRA72x
17 baseclass_code should be 0xff
H A Dpci-ntb.rst12 vendorid should be 0x104c
13 deviceid should be 0xb00d for TI's J721E SoC
16 subclass_code should be 0x00
17 baseclass_code should be 0x5
/openbmc/linux/include/linux/mmc/
H A Dsdio_ids.h13 #define SDIO_CLASS_NONE 0x00 /* Not a SDIO standard interface */
14 #define SDIO_CLASS_UART 0x01 /* standard UART interface */
15 #define SDIO_CLASS_BT_A 0x02 /* Type-A BlueTooth std interface */
16 #define SDIO_CLASS_BT_B 0x03 /* Type-B BlueTooth std interface */
17 #define SDIO_CLASS_GPS 0x04 /* GPS standard interface */
18 #define SDIO_CLASS_CAMERA 0x05 /* Camera standard interface */
19 #define SDIO_CLASS_PHS 0x06 /* PHS standard interface */
20 #define SDIO_CLASS_WLAN 0x07 /* WLAN interface */
21 #define SDIO_CLASS_ATA 0x08 /* Embedded SDIO-ATA std interface */
22 #define SDIO_CLASS_BT_AMP 0x09 /* Type-A Bluetooth AMP interface */
[all …]
/openbmc/linux/drivers/clk/qcom/
H A Ddispcc-sm6375.c39 { 249600000, 2000000000, 0 },
44 .l = 0x20,
45 .alpha = 0x800,
46 .config_ctl_val = 0x20485699,
47 .config_ctl_hi_val = 0x00002261,
48 .config_ctl_hi1_val = 0x329a299c,
49 .user_ctl_val = 0x00000001,
50 .user_ctl_hi_val = 0x00000805,
51 .user_ctl_hi1_val = 0x00000000,
55 .offset = 0x0,
[all …]
H A Ddispcc-sm6350.c35 { 249600000, 2000000000, 0 },
39 .l = 0x3a,
40 .alpha = 0x5555,
41 .config_ctl_val = 0x20485699,
42 .config_ctl_hi_val = 0x00002067,
43 .test_ctl_val = 0x40000000,
44 .test_ctl_hi_val = 0x00000002,
45 .user_ctl_val = 0x00000000,
46 .user_ctl_hi_val = 0x00004805,
50 .offset = 0x0,
[all …]
H A Ddispcc-sc7280.c34 { 249600000, 2000000000, 0 },
39 .l = 0x4F,
40 .alpha = 0x2AAA,
41 .config_ctl_val = 0x20485699,
42 .config_ctl_hi_val = 0x00002261,
43 .config_ctl_hi1_val = 0x329A299C,
44 .user_ctl_val = 0x00000001,
45 .user_ctl_hi_val = 0x00000805,
46 .user_ctl_hi1_val = 0x00000000,
50 .offset = 0x0,
[all …]
H A Dmmcc-msm8994.c44 { P_XO, 0 },
54 { P_XO, 0 },
64 { P_XO, 0 },
76 { P_XO, 0 },
91 { 1500000000, 2000000000, 0 },
95 { 500000000, 1500000000, 0 },
99 .post_div_mask = 0xf00,
103 .offset = 0x0,
108 .enable_reg = 0x100,
109 .enable_mask = BIT(0),
[all …]
H A Dmmcc-msm8998.c49 { 0x0, 1 },
50 { 0x1, 2 },
51 { 0x3, 4 },
52 { 0x7, 8 },
57 .offset = 0xc000,
60 .enable_reg = 0x1e0,
61 .enable_mask = BIT(0),
74 .offset = 0xc000,
89 .offset = 0xc050,
92 .enable_reg = 0x1e0,
[all …]
/openbmc/qemu/include/hw/pci/
H A Dpci_ids.h16 #define PCI_CLASS_NOT_DEFINED 0x0000
17 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
19 #define PCI_BASE_CLASS_STORAGE 0x01
20 #define PCI_CLASS_STORAGE_SCSI 0x0100
21 #define PCI_CLASS_STORAGE_IDE 0x0101
22 #define PCI_CLASS_STORAGE_FLOPPY 0x0102
23 #define PCI_CLASS_STORAGE_IPI 0x0103
24 #define PCI_CLASS_STORAGE_RAID 0x0104
25 #define PCI_CLASS_STORAGE_ATA 0x0105
26 #define PCI_CLASS_STORAGE_SATA 0x0106
[all …]
/openbmc/linux/Documentation/PCI/endpoint/
H A Dpci-ntb-howto.rst66 baseclass_code deviceid msi_interrupts pci-epf-ntb.0
73 vendorid with 0xffff and interrupt_pin with 0x0001::
76 0xffff
78 0x0001
88 # echo 0x104c > functions/pci_epf_ntb/func1/vendorid
89 # echo 0xb00d > functions/pci_epf_ntb/func1/deviceid
96 # ls functions/pci_epf_ntb/func1/pci_epf_ntb.0/
102 # echo 4 > functions/pci_epf_ntb/func1/pci_epf_ntb.0/db_count
103 # echo 128 > functions/pci_epf_ntb/func1/pci_epf_ntb.0/spad_count
104 # echo 2 > functions/pci_epf_ntb/func1/pci_epf_ntb.0/num_mws
[all …]
H A Dpci-test-howto.rst67 vendorid with 0xffff and interrupt_pin with 0x0001::
70 0xffff
72 0x0001
82 # echo 0x104c > functions/pci_epf_test/func1/vendorid
83 # echo 0xb500 > functions/pci_epf_test/func1/deviceid
/openbmc/qemu/tests/qtest/
H A Dnpcm_gmac-test.c27 #define PCS_BASE_ADDRESS 0xf0780000
28 #define NPCM_PCS_IND_AC_BA 0x1fe
43 .base_addr = 0xf0802000
47 .base_addr = 0xf0804000
56 g_assert_true(diff >= 0 && diff < ARRAY_SIZE(gmac_module_list)); in gmac_module_index()
64 NPCM_DMA_BUS_MODE = 0x1000,
65 NPCM_DMA_XMT_POLL_DEMAND = 0x1004,
66 NPCM_DMA_RCV_POLL_DEMAND = 0x1008,
67 NPCM_DMA_RCV_BASE_ADDR = 0x100c,
68 NPCM_DMA_TX_BASE_ADDR = 0x1010,
[all …]
/openbmc/linux/drivers/misc/mei/
H A Dhw-txe-regs.h30 #define PCI_CFG_TXE_FW_STS0 0x40
31 # define PCI_CFG_TXE_FW_STS0_WRK_ST_MSK 0x0000000F
32 # define PCI_CFG_TXE_FW_STS0_OP_ST_MSK 0x000001C0
33 # define PCI_CFG_TXE_FW_STS0_FW_INIT_CMPLT 0x00000200
34 # define PCI_CFG_TXE_FW_STS0_ERR_CODE_MSK 0x0000F000
35 # define PCI_CFG_TXE_FW_STS0_OP_MODE_MSK 0x000F0000
36 # define PCI_CFG_TXE_FW_STS0_RST_CNT_MSK 0x00F00000
37 #define PCI_CFG_TXE_FW_STS1 0x48
39 #define IPC_BASE_ADDR 0x80400 /* SeC IPC Base Address */
42 #define SEC_IPC_INPUT_DOORBELL_REG (0x0000 + IPC_BASE_ADDR)
[all …]
/openbmc/linux/drivers/net/fddi/skfp/h/
H A Dsmt_p.h19 #define SMT_P0012 0x0012
21 #define SMT_P0015 0x0015
22 #define SMT_P0016 0x0016
23 #define SMT_P0017 0x0017
24 #define SMT_P0018 0x0018
25 #define SMT_P0019 0x0019
27 #define SMT_P001A 0x001a
28 #define SMT_P001B 0x001b
29 #define SMT_P001C 0x001c
30 #define SMT_P001D 0x001d
[all …]
/openbmc/linux/drivers/mmc/core/
H A Dcard.h20 #define MMC_STATE_PRESENT (1<<0) /* present in sysfs */
81 #define CID_MANFID_SANDISK 0x2
82 #define CID_MANFID_SANDISK_SD 0x3
83 #define CID_MANFID_ATP 0x9
84 #define CID_MANFID_TOSHIBA 0x11
85 #define CID_MANFID_GIGASTONE 0x12
86 #define CID_MANFID_MICRON 0x13
87 #define CID_MANFID_SAMSUNG 0x15
88 #define CID_MANFID_APACER 0x27
89 #define CID_MANFID_KINGSTON 0x70
[all …]
/openbmc/linux/drivers/media/pci/cx25821/
H A Dcx25821-medusa-reg.h13 #define HOST_REGISTER1 0x0000
14 #define HOST_REGISTER2 0x0001
17 #define CHIP_CTRL 0x0100
18 #define AFE_AB_CTRL 0x0104
19 #define AFE_CD_CTRL 0x0108
20 #define AFE_EF_CTRL 0x010C
21 #define AFE_GH_CTRL 0x0110
22 #define DENC_AB_CTRL 0x0114
23 #define BYP_AB_CTRL 0x0118
24 #define MON_A_CTRL 0x011C
[all …]
/openbmc/linux/arch/sh/include/asm/
H A Dhd64461.h10 * (please note manual reference 0x10000000 = 0xb0000000)
14 #define HD64461_PCC_WINDOW 0x01000000
16 /* Area 6 - Slot 0 - memory and/or IO card */
17 #define HD64461_IOBASE 0xb0000000
19 #define HD64461_PCC0_BASE HD64461_IO_OFFSET(0x8000000)
20 #define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */
21 #define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */
22 #define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */
25 #define HD64461_PCC1_BASE HD64461_IO_OFFSET(0x4000000)
26 #define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */
[all …]
/openbmc/qemu/include/hw/ppc/
H A Dspapr_nested.h7 #define GSB_HV_VCPU_IGNORED_ID 0x0000 /* An element whose value is ignored */
8 #define GSB_HV_VCPU_STATE_SIZE 0x0001 /* HV internal format VCPU state size */
9 #define GSB_VCPU_OUT_BUF_MIN_SZ 0x0002 /* Min size of the Run VCPU o/p buffer */
10 #define GSB_VCPU_LPVR 0x0003 /* Logical PVR */
11 #define GSB_TB_OFFSET 0x0004 /* Timebase Offset */
12 #define GSB_PART_SCOPED_PAGETBL 0x0005 /* Partition Scoped Page Table */
13 #define GSB_PROCESS_TBL 0x0006 /* Process Table */
14 /* RESERVED 0x0007 - 0x0BFF */
15 #define GSB_VCPU_IN_BUFFER 0x0C00 /* Run VCPU Input Buffer */
16 #define GSB_VCPU_OUT_BUFFER 0x0C01 /* Run VCPU Out Buffer */
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2g-ice.dts18 reg = <0x00000008 0x00000000 0x00000000 0x20000000>;
28 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
128 <&pca9536 0 GPIO_ACTIVE_HIGH>;
129 linux,axis = <0>; /* ABS_X */
136 pinctrl-0 = <&user_leds>;
223 K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */
224 K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
230 K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
231 K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
232 K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
[all …]
/openbmc/linux/drivers/net/ethernet/intel/e1000e/
H A Dhw.h12 #define E1000_DEV_ID_82571EB_COPPER 0x105E
13 #define E1000_DEV_ID_82571EB_FIBER 0x105F
14 #define E1000_DEV_ID_82571EB_SERDES 0x1060
15 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
16 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
17 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
18 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
19 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
20 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
21 #define E1000_DEV_ID_82572EI_COPPER 0x107D
[all …]
/openbmc/u-boot/drivers/virtio/
H A Dvirtio_pci_modern.c21 /* PCI device ID in the range 0x1040 to 0x107f */
22 #define VIRTIO_PCI_VENDOR_ID 0x1af4
23 #define VIRTIO_PCI_DEVICE_ID00 0x1040
24 #define VIRTIO_PCI_DEVICE_ID01 0x1041
25 #define VIRTIO_PCI_DEVICE_ID02 0x1042
26 #define VIRTIO_PCI_DEVICE_ID03 0x1043
27 #define VIRTIO_PCI_DEVICE_ID04 0x1044
28 #define VIRTIO_PCI_DEVICE_ID05 0x1045
29 #define VIRTIO_PCI_DEVICE_ID06 0x1046
30 #define VIRTIO_PCI_DEVICE_ID07 0x1047
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721e-main.dtsi15 #clock-cells = <0>;
17 clock-frequency = <0>;
21 #clock-cells = <0>;
23 clock-frequency = <0>;
30 reg = <0x0 0x70000000 0x0 0x800000>;
33 ranges = <0x0 0x0 0x70000000 0x800000>;
35 atf-sram@0 {
36 reg = <0x0 0x20000>;
42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
45 ranges = <0x0 0x0 0x00100000 0x1c000>;
[all …]
/openbmc/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi.h10 #define HDMI_DESIGN_ID 0x0000
11 #define HDMI_REVISION_ID 0x0001
12 #define HDMI_PRODUCT_ID0 0x0002
13 #define HDMI_PRODUCT_ID1 0x0003
14 #define HDMI_CONFIG0_ID 0x0004
15 #define HDMI_CONFIG1_ID 0x0005
16 #define HDMI_CONFIG2_ID 0x0006
17 #define HDMI_CONFIG3_ID 0x0007
20 #define HDMI_IH_FC_STAT0 0x0100
21 #define HDMI_IH_FC_STAT1 0x0101
[all …]

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