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Searched +full:0 +full:x10014000 (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dfsl-imx-mmc.yaml47 reg = <0x10014000 0x1000>;
/openbmc/qemu/hw/arm/
H A Drealview.c35 #define SMP_BOOT_ADDR 0xe0000000
36 #define SMP_BOOTREG_ADDR 0x10000030
56 0x33b,
57 0x33b,
58 0x769,
59 0x76d
70 qdev_connect_gpio_out(splitter, 0, out1); in split_irq_from_named()
72 qdev_connect_gpio_out_named(src, outname, 0, in split_irq_from_named()
73 qdev_get_gpio_in(splitter, 0)); in split_irq_from_named()
95 int is_mpcore = 0; in realview_init()
[all …]
/openbmc/u-boot/include/configs/
H A Dapf27.h30 #define CONFIG_SPL_TEXT_BASE 0xA0000000
34 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
36 #define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800
54 #define PHYS_SDRAM_1 0xA0000000
55 #define PHYS_SDRAM_2 0xB0000000
58 #define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */
59 #define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */
62 + PHYS_SDRAM_1_SIZE - 0x0100000)
67 #define ACFG_MONITOR_OFFSET 0x00000000
68 #define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */
[all …]
/openbmc/linux/drivers/net/wwan/t7xx/
H A Dt7xx_reg.h25 #define MHCCIF_RC_DEV_BASE 0x10024000
27 #define REG_RC2EP_SW_BSY 0x04
28 #define REG_RC2EP_SW_INT_START 0x08
30 #define REG_RC2EP_SW_TCHNUM 0x0c
42 #define REG_EP2RC_SW_INT_STS 0x10
43 #define REG_EP2RC_SW_INT_ACK 0x14
44 #define REG_EP2RC_SW_INT_EAP_MASK 0x20
45 #define REG_EP2RC_SW_INT_EAP_MASK_SET 0x30
46 #define REG_EP2RC_SW_INT_EAP_MASK_CLR 0x40
48 #define D2H_INT_DS_LOCK_ACK BIT(0)
[all …]
/openbmc/qemu/hw/riscv/
H A Dsifive_e.c8 * 0) UART
15 * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000.
52 [SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 },
53 [SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 },
54 [SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 },
55 [SIFIVE_E_DEV_CLINT] = { 0x2000000, 0x10000 },
56 [SIFIVE_E_DEV_PLIC] = { 0xc000000, 0x4000000 },
57 [SIFIVE_E_DEV_AON] = { 0x10000000, 0x8000 },
58 [SIFIVE_E_DEV_PRCI] = { 0x10008000, 0x8000 },
59 [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000, 0x1000 },
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Darm-realview-eb.dtsi43 /* 128 MiB memory @ 0x0 */
44 reg = <0x00000000 0x08000000>;
48 vmmc: fixedregulator@0 {
57 #clock-cells = <0>;
63 #clock-cells = <0>;
71 #clock-cells = <0>;
79 #clock-cells = <0>;
87 #clock-cells = <0>;
95 #clock-cells = <0>;
103 #clock-cells = <0>;
[all …]
H A Darm-realview-pbx.dtsi44 /* 128 MiB memory @ 0x0 */
45 reg = <0x00000000 0x08000000>;
66 #clock-cells = <0>;
72 #clock-cells = <0>;
78 #clock-cells = <0>;
86 #clock-cells = <0>;
94 #clock-cells = <0>;
102 #clock-cells = <0>;
110 #clock-cells = <0>;
118 #clock-cells = <0>;
[all …]
H A Darm-realview-pb1176.dts45 /* 128 MiB memory @ 0x0 */
46 reg = <0x00000000 0x08000000>;
67 #clock-cells = <0>;
73 #clock-cells = <0>;
81 #clock-cells = <0>;
89 #clock-cells = <0>;
97 #clock-cells = <0>;
105 #clock-cells = <0>;
113 pclk: pclk@0 {
114 #clock-cells = <0>;
[all …]
H A Darm-realview-pb11mp.dts45 * The PB11MPCore has 512 MiB memory @ 0x70000000
46 * and the first 256 are also remapped @ 0x00000000
48 reg = <0x70000000 0x20000000>;
53 #size-cells = <0>;
56 MP11_0: cpu@0 {
59 reg = <0>;
91 reg = <0x1f001000 0x1000>,
92 <0x1f000100 0x100>;
97 reg = <0x1f002000 0x1000>;
99 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx27.dtsi47 reg = <0x10040000 0x1000>;
53 #clock-cells = <0>;
59 #size-cells = <0>;
62 cpu: cpu@0 {
64 reg = <0>;
88 reg = <0x10000000 0x20000>;
93 reg = <0x10001000 0x1000>;
104 reg = <0x10002000 0x1000>;
111 reg = <0x10003000 0x1000>;
120 reg = <0x10004000 0x1000>;
[all …]
/openbmc/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main.c55 { TARGET_CPU, 0, 0 }, /* 0x600000000 */
56 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */
57 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */
58 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */
59 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */
60 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */
61 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */
62 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */
63 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */
64 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */
[all …]