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/openbmc/u-boot/arch/arm/include/asm/arch-mx7/
H A Dcrm_regs.h15 #define CCM_GPR0_OFFSET 0x0
16 #define CCM_OBSERVE0_OFFSET 0x0400
17 #define CCM_SCTRL0_OFFSET 0x0800
18 #define CCM_CCGR0_OFFSET 0x4000
19 #define CCM_ROOT0_TARGET_OFFSET 0x8000
58 struct mxc_ccm_ccgr ccgr_array[191]; /* offset 0x4000 */
60 struct mxc_ccm_root_slice root[121]; /* offset 0x8000 */
65 uint32_t ctrl_24m; /* offset 0x0000 */
69 uint32_t rcosc_config0; /* offset 0x0010 */
73 uint32_t rcosc_config1; /* offset 0x0020 */
[all …]
/openbmc/linux/drivers/mtd/maps/
H A Dscx200_docflash.c27 static int probe = 0; /* Don't autoprobe */
28 static unsigned size = 0x1000000; /* 16 MiB the whole ISA address space */
32 module_param(probe, int, 0);
34 module_param(size, int, 0);
36 module_param(width, int, 0);
38 module_param(flashtype, charp, 0);
51 .offset = 0,
52 .size = 0xc0000
56 .offset = 0xc0000,
57 .size = 0x40000
[all …]
/openbmc/u-boot/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h10 unsigned int pid; /* 0x00 */
11 unsigned char rsvd0[224]; /* 0x04 */
12 unsigned int rstype; /* 0xe4 */
13 unsigned char rsvd1[24]; /* 0xe8 */
14 unsigned int pllctl; /* 0x100 */
15 unsigned char rsvd2[4]; /* 0x104 */
16 unsigned int secctl; /* 0x108 */
17 unsigned int rv; /* 0x10c */
18 unsigned int pllm; /* 0x110 */
19 unsigned int prediv; /* 0x114 */
[all …]
/openbmc/linux/arch/sh/boards/mach-microdev/
H A Dsetup.c21 [0] = {
22 .start = 0x300,
23 .end = 0x300 + SZ_4K - 1,
41 { S1DREG_MISC, 0x00 },
42 { S1DREG_COM_DISP_MODE, 0x00 },
43 { S1DREG_GPIO_CNF0, 0x00 },
44 { S1DREG_GPIO_CNF1, 0x00 },
45 { S1DREG_GPIO_CTL0, 0x00 },
46 { S1DREG_GPIO_CTL1, 0x00 },
47 { S1DREG_CLK_CNF, 0x02 },
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dste-db8520.dtsi8 operating-points = <1152000 0
9 798720 0
10 399360 0
11 199680 0>;
22 reg = <0x06000000 0x00f00000>;
28 reg = <0x06f00000 0x00100000>;
34 reg = <0x07000000 0x01000000>;
48 reg = <0x17f00000 0x00100000>;
H A Dste-db8500.dtsi8 operating-points = <998400 0
9 798720 0
10 399360 0
11 199680 0>;
22 reg = <0x06000000 0x00f00000>;
28 reg = <0x06f00000 0x00100000>;
34 reg = <0x07000000 0x01000000>;
48 reg = <0x17f00000 0x00100000>;
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun50i_h6.h11 #define SUNXI_SRAM_C_BASE 0x00028000
12 #define SUNXI_SRAM_A2_BASE 0x00100000
14 #define SUNXI_DE3_BASE 0x01000000
15 #define SUNXI_SS_BASE 0x01904000
16 #define SUNXI_EMCE_BASE 0x01905000
18 #define SUNXI_SRAMC_BASE 0x03000000
19 #define SUNXI_CCM_BASE 0x03001000
20 #define SUNXI_DMA_BASE 0x03002000
21 /* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */
22 #define SUNXI_SIDC_BASE 0x03006000
[all …]
H A Dcpu_sun9i.h12 #define REGS_AHB0_BASE 0x01C00000
13 #define REGS_AHB1_BASE 0x00800000
14 #define REGS_AHB2_BASE 0x03000000
15 #define REGS_APB0_BASE 0x06000000
16 #define REGS_APB1_BASE 0x07000000
17 #define REGS_RCPUS_BASE 0x08000000
19 #define SUNXI_SRAM_D_BASE 0x08100000
22 #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
23 #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
25 #define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dclock.h39 MXC_ARM_CLK = 0,
40 ARM_A53_CLK_ROOT = 0,
179 CCGR_DVFS = 0,
286 CLK_SRC_CKIL_SYNC_REQ = 0,
330 CLK_ROOT_PRE_DIV1 = 0,
341 CLK_ROOT_POST_DIV1 = 0,
469 #define CCGR_CLK_ON_MASK 0x03
470 #define CLK_SRC_ON_MASK 0x03
473 #define CLK_ROOT_OFF (0 << 28)
476 #define CLK_ROOT_SOURCE_SEL(n) (((n) & 0x7) << 24)
[all …]
/openbmc/linux/drivers/edac/
H A Dfsl_ddr_edac.h24 #define FSL_MC_DDR_SDRAM_CFG 0x0110
25 #define FSL_MC_CS_BNDS_0 0x0000
26 #define FSL_MC_CS_BNDS_OFS 0x0008
28 #define FSL_MC_DATA_ERR_INJECT_HI 0x0e00
29 #define FSL_MC_DATA_ERR_INJECT_LO 0x0e04
30 #define FSL_MC_ECC_ERR_INJECT 0x0e08
31 #define FSL_MC_CAPTURE_DATA_HI 0x0e20
32 #define FSL_MC_CAPTURE_DATA_LO 0x0e24
33 #define FSL_MC_CAPTURE_ECC 0x0e28
34 #define FSL_MC_ERR_DETECT 0x0e40
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dreg_8xx.h29 #define SPRN_EID 81 /* External interrupt disable (EE=0, RI=1) */
30 #define SPRN_NRI 82 /* Non recoverable interrupt (EE=0, RI=0) */
38 #define LCTRL1_CTE_GT 0xc0000000
39 #define LCTRL1_CTF_LT 0x14000000
40 #define LCTRL1_CRWE_RW 0x00000000
41 #define LCTRL1_CRWE_RO 0x00040000
42 #define LCTRL1_CRWE_WO 0x000c0000
43 #define LCTRL1_CRWF_RW 0x00000000
44 #define LCTRL1_CRWF_RO 0x00010000
45 #define LCTRL1_CRWF_WO 0x00030000
[all …]
/openbmc/linux/arch/arm/boot/dts/nuvoton/
H A Dnuvoton-wpcm450-supermicro-x9sci-ln4f.dts7 /memreserve/ 0x07000000 0x01000000;
27 memory@0 {
29 reg = <0 0x08000000>; /* 128 MiB */
35 pinctrl-0 = <&key_pins>;
47 pinctrl-0 = <&led_pins>;
64 flash@0 {
65 reg = <0>;
72 /* 0 */ "", "host-reset-control-n", "", "", "", "", "", "",
78 /* 0 */ "", "", "", "", "led-heartbeat", "", "", "led-uid",
84 /* 0 */ "", "", "", "", "", "", "", "",
/openbmc/u-boot/arch/arm/dts/
H A Dstm32mp15-ddr3-2x4Gb-1066-binG.dtsi13 * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G
22 #define DDR_MEM_SIZE 0x40000000
24 #define DDR_MSTR 0x00040401
25 #define DDR_MRCTRL0 0x00000010
26 #define DDR_MRCTRL1 0x00000000
27 #define DDR_DERATEEN 0x00000000
28 #define DDR_DERATEINT 0x00800000
29 #define DDR_PWRCTL 0x00000000
30 #define DDR_PWRTMG 0x00400010
31 #define DDR_HWLPCTL 0x00000000
[all …]
/openbmc/linux/drivers/net/wireless/silabs/wfx/
H A Dhwio.h33 #define CFG_ERR_SPI_FRAME 0x00000001 /* only with SPI */
34 #define CFG_ERR_SDIO_BUF_MISMATCH 0x00000001 /* only with SDIO */
35 #define CFG_ERR_BUF_UNDERRUN 0x00000002
36 #define CFG_ERR_DATA_IN_TOO_LARGE 0x00000004
37 #define CFG_ERR_HOST_NO_OUT_QUEUE 0x00000008
38 #define CFG_ERR_BUF_OVERRUN 0x00000010
39 #define CFG_ERR_DATA_OUT_TOO_LARGE 0x00000020
40 #define CFG_ERR_HOST_NO_IN_QUEUE 0x00000040
41 #define CFG_ERR_HOST_CRC_MISS 0x00000080 /* only with SDIO */
42 #define CFG_SPI_IGNORE_CS 0x00000080 /* only with SPI */
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm953012hr.dts50 reg = <0x80000000 0x10000000>;
55 partition@0 {
57 reg = <0x00000000 0x00200000>;
62 reg = <0x00200000 0x00400000>;
66 reg = <0x00600000 0x00a00000>;
70 reg = <0x01000000 0x07000000>;
82 partition@0 {
84 reg = <0x00000000 0x000d0000>;
88 reg = <0x000d0000 0x00030000>;
92 reg = <0x00100000 0x00600000>;
[all …]
H A Dbcm953012k.dts48 reg = <0x80000000 0x10000000>;
53 nand@0 {
55 reg = <0>;
64 partition@0 {
66 reg = <0x00000000 0x00200000>;
71 reg = <0x00200000 0x00400000>;
75 reg = <0x00600000 0x00a00000>;
79 reg = <0x01000000 0x07000000>;
92 partition@0 {
94 reg = <0x00000000 0x000d0000>;
[all …]
/openbmc/u-boot/include/
H A Dfsl_ddr_sdram.h27 #define DDR3_RTT_OFF 0
34 #define DDR4_RTT_OFF 0
43 #define DDR2_RTT_OFF 0
73 #define FSL_DDR_ODT_NEVER 0x0
74 #define FSL_DDR_ODT_CS 0x1
75 #define FSL_DDR_ODT_ALL_OTHER_CS 0x2
76 #define FSL_DDR_ODT_OTHER_DIMM 0x3
77 #define FSL_DDR_ODT_ALL 0x4
78 #define FSL_DDR_ODT_SAME_DIMM 0x5
79 #define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6
[all …]
/openbmc/linux/drivers/scsi/mpi3mr/mpi/
H A Dmpi30_init.h38 #define MPI3_SCSIIO_MSGFLAGS_METASGL_VALID (0x80)
39 #define MPI3_SCSIIO_MSGFLAGS_DIVERT_TO_FIRMWARE (0x40)
40 #define MPI3_SCSIIO_FLAGS_LARGE_CDB (0x60000000)
41 #define MPI3_SCSIIO_FLAGS_CDB_16_OR_LESS (0x00000000)
42 #define MPI3_SCSIIO_FLAGS_CDB_GREATER_THAN_16 (0x20000000)
43 #define MPI3_SCSIIO_FLAGS_CDB_IN_SEPARATE_BUFFER (0x40000000)
44 #define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_MASK (0x07000000)
45 #define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_SIMPLEQ (0x00000000)
46 #define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_HEADOFQ (0x01000000)
47 #define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_ORDEREDQ (0x02000000)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dexynos-srom.yaml35 <bank-number> 0 <parent address of bank> <size>
39 "^.*@[0-3],[a-f0-9]+$":
53 typically 0 as this is the start of the bank.
77 Tacp: Page mode access cycle at Page mode (0 - 15)
78 Tcah: Address holding time after CSn (0 - 15)
79 Tcoh: Chip selection hold on OEn (0 - 15)
80 Tacc: Access cycle (0 - 31, the actual time is N + 1)
81 Tcos: Chip selection set-up before OEn (0 - 15)
82 Tacs: Address set-up before CSn (0 - 15)
99 reg = <0x12560000 0x14>;
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dcache.h67 #define CACHECRBA 0x80000823 /* Cache configuration register address */
68 #define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
69 #define L2CACHE_512KB 0x00 /* 512KB */
70 #define L2CACHE_256KB 0x01 /* 256KB */
71 #define L2CACHE_1MB 0x02 /* 1MB */
72 #define L2CACHE_NONE 0x03 /* NONE */
73 #define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
88 #define IDC_ENABLE 0x02000000 /* Cache enable */
89 #define IDC_DISABLE 0x04000000 /* Cache disable */
90 #define IDC_LDLCK 0x06000000 /* Load and lock */
[all …]
/openbmc/linux/include/linux/bcma/
H A Dbcma_regs.h7 #define BCMA_CLKCTLST 0x01E0 /* Clock control and status */
8 #define BCMA_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
9 #define BCMA_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
10 #define BCMA_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
11 #define BCMA_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
12 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
13 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
14 #define BCMA_CLKCTLST_HQCLKREQ 0x00000040 /* HQ Clock */
15 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
17 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
/openbmc/u-boot/include/configs/
H A Ddevkit8000.h23 * header. That is 0x800FFFC0--0x80100000 should not be used for any
27 #define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
28 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
30 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
31 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
49 #define CONFIG_DM9000_BASE 0x2c000000
51 #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
63 #define CONFIG_JFFS2_PART_OFFSET 0x680000
64 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
77 "loadaddr=0x82000000\0" \
[all …]
H A Dvf610twr.h42 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
48 #define CONFIG_FEC_MXC_PHYADDR 0
63 #define CONFIG_SYS_SPD_BUS_NUM 0
66 #define CONFIG_SYS_LOAD_ADDR 0x82000000
82 "bootm_size=0x07000000\0" \
83 "loadaddr=0x82000000\0" \
84 "kernel_addr_r=0x82000000\0" \
85 "fdt_addr=0x84000000\0" \
86 "fdt_addr_r=0x84000000\0" \
87 "rdaddr=0x84080000\0" \
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dsiul.h11 #define SIUL2_MIDR1 (SIUL2_BASE_ADDR + 0x00000004)
12 #define SIUL2_MIDR2 (SIUL2_BASE_ADDR + 0x00000008)
13 #define SIUL2_DISR0 (SIUL2_BASE_ADDR + 0x00000010)
14 #define SIUL2_DIRER0 (SIUL2_BASE_ADDR + 0x00000018)
15 #define SIUL2_DIRSR0 (SIUL2_BASE_ADDR + 0x00000020)
16 #define SIUL2_IREER0 (SIUL2_BASE_ADDR + 0x00000028)
17 #define SIUL2_IFEER0 (SIUL2_BASE_ADDR + 0x00000030)
18 #define SIUL2_IFER0 (SIUL2_BASE_ADDR + 0x00000038)
20 #define SIUL2_IFMCR_BASE (SIUL2_BASE_ADDR + 0x00000040)
23 #define SIUL2_IFCPR (SIUL2_BASE_ADDR + 0x000000C0)
[all …]

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