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/openbmc/u-boot/arch/arm/include/asm/arch-mx7/
H A Dcrm_regs.h15 #define CCM_GPR0_OFFSET 0x0
16 #define CCM_OBSERVE0_OFFSET 0x0400
17 #define CCM_SCTRL0_OFFSET 0x0800
18 #define CCM_CCGR0_OFFSET 0x4000
19 #define CCM_ROOT0_TARGET_OFFSET 0x8000
58 struct mxc_ccm_ccgr ccgr_array[191]; /* offset 0x4000 */
60 struct mxc_ccm_root_slice root[121]; /* offset 0x8000 */
65 uint32_t ctrl_24m; /* offset 0x0000 */
69 uint32_t rcosc_config0; /* offset 0x0010 */
73 uint32_t rcosc_config1; /* offset 0x0020 */
[all …]
/openbmc/u-boot/arch/xtensa/dts/
H A Dxtfpga-flash-128m.dtsi7 reg = <0x00000000 0x08000000>;
10 partition@0x0 {
12 reg = <0x00000000 0x06000000>;
14 partition@0x6000000 {
16 reg = <0x06000000 0x00800000>;
18 partition@0x6800000 {
20 reg = <0x06800000 0x017e0000>;
22 partition@0x7fe0000 {
24 reg = <0x07fe0000 0x00020000>;
/openbmc/linux/arch/xtensa/boot/dts/
H A Dxtfpga-flash-128m.dtsi8 reg = <0x00000000 0x08000000>;
11 partition@0 {
13 reg = <0x00000000 0x06000000>;
17 reg = <0x06000000 0x00800000>;
21 reg = <0x06800000 0x017e0000>;
25 reg = <0x07fe0000 0x00020000>;
H A Dlx200mx.dts8 memory@0 {
10 reg = <0x00000000 0x06000000>;
/openbmc/linux/arch/sh/include/mach-common/mach/
H A Dsh7785lcr.h11 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
12 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
13 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C
14 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
15 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
16 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
17 * 0x14000000 - 0x17ffffff(CS5) | reserved | USB
18 * 0x18000000 - 0x1bffffff(CS6) | reserved | SD
19 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
23 #define NOR_FLASH_ADDR 0x00000000
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dconfig.h13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
20 #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
25 #define CONFIG_SYS_PAGE_SIZE 0x10000
31 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
32 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
33 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
48 #define GICD_BASE 0x06000000
49 #define GICR_BASE 0x06100000
52 #define SMMU_BASE 0x05000000 /* GR0 Base */
69 #define CCI_MN_BASE 0x04000000
[all …]
/openbmc/openbmc/meta-nuvoton/dynamic-layers/arm-layer/recipes-security/optee/
H A Doptee-os_%.bbappend4 CFG_TZDRAM_START=0x02100000 \
5 CFG_TZDRAM_SIZE=0x03f00000 \
6 CFG_SHMEM_START=0x06000000 \
7 CFG_TEE_SDP_MEM_BASE=0x05F00000 \
8 CFG_TEE_SDP_MEM_SIZE=0x00100000 \
/openbmc/linux/arch/sh/boards/
H A Dboard-urquell.c32 * SW2 0x1x xxxx -> little endian
39 * 0x00000000 - 0x04000000 (CS0) Nor Flash
40 * 0x04000000 - 0x04200000 (CS1) SRAM
41 * 0x05000000 - 0x05800000 (CS1) on board register
42 * 0x05800000 - 0x06000000 (CS1) LAN91C111
43 * 0x06000000 - 0x06400000 (CS1) PCMCIA
44 * 0x08000000 - 0x10000000 (CS2-CS3) DDR3
45 * 0x10000000 - 0x14000000 (CS4) PCIe
46 * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM
47 * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM
[all …]
/openbmc/u-boot/board/cadence/xtfpga/
H A DKconfig33 default 0x04000000 if XTFPGA_LX60
34 default 0x03000000 if XTFPGA_LX110
35 default 0x06000000 if XTFPGA_LX200
36 default 0x18000000 if XTFPGA_ML605
37 default 0x38000000 if XTFPGA_KC705
/openbmc/u-boot/board/freescale/mx35pdk/
H A Dmx35pdk.h13 #define DBG_CSCR_U_CONFIG 0x0000D843
14 #define DBG_CSCR_L_CONFIG 0x22252521
15 #define DBG_CSCR_A_CONFIG 0x22220A00
17 #define CCM_CCMR_CONFIG 0x003F4208
18 #define CCM_PDR0_CONFIG 0x00801000
21 #define ESDCTL_0x92220000 0x92220000
22 #define ESDCTL_0xA2220000 0xA2220000
23 #define ESDCTL_0xB2220000 0xB2220000
24 #define ESDCTL_0x82228080 0x82228080
26 #define ESDCTL_PRECHARGE 0x00000400
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dste-db8520.dtsi8 operating-points = <1152000 0
9 798720 0
10 399360 0
11 199680 0>;
22 reg = <0x06000000 0x00f00000>;
28 reg = <0x06f00000 0x00100000>;
34 reg = <0x07000000 0x01000000>;
48 reg = <0x17f00000 0x00100000>;
H A Dste-db8500.dtsi8 operating-points = <998400 0
9 798720 0
10 399360 0
11 199680 0>;
22 reg = <0x06000000 0x00f00000>;
28 reg = <0x06f00000 0x00100000>;
34 reg = <0x07000000 0x01000000>;
48 reg = <0x17f00000 0x00100000>;
/openbmc/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_debug.h11 I40E_DEBUG_INIT = 0x00000001,
12 I40E_DEBUG_RELEASE = 0x00000002,
14 I40E_DEBUG_LINK = 0x00000010,
15 I40E_DEBUG_PHY = 0x00000020,
16 I40E_DEBUG_HMC = 0x00000040,
17 I40E_DEBUG_NVM = 0x00000080,
18 I40E_DEBUG_LAN = 0x00000100,
19 I40E_DEBUG_FLOW = 0x00000200,
20 I40E_DEBUG_DCB = 0x00000400,
21 I40E_DEBUG_DIAG = 0x00000800,
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun50i_h6.h11 #define SUNXI_SRAM_C_BASE 0x00028000
12 #define SUNXI_SRAM_A2_BASE 0x00100000
14 #define SUNXI_DE3_BASE 0x01000000
15 #define SUNXI_SS_BASE 0x01904000
16 #define SUNXI_EMCE_BASE 0x01905000
18 #define SUNXI_SRAMC_BASE 0x03000000
19 #define SUNXI_CCM_BASE 0x03001000
20 #define SUNXI_DMA_BASE 0x03002000
21 /* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */
22 #define SUNXI_SIDC_BASE 0x03006000
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721e.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xC000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xC000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
114 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
/openbmc/u-boot/include/configs/
H A Dxtfpga.h35 #define CONFIG_SYS_IO_BASE 0xf0000000
37 #define CONFIG_SYS_MEMORY_BASE 0x60000000
38 #define CONFIG_SYS_IO_BASE 0x90000000
39 #define CONFIG_MAX_MEM_MAPPED 0x10000000
44 * LX60 0x04000000 64 MB
45 * LX110 0x03000000 48 MB
46 * LX200 0x06000000 96 MB
47 * ML605 0x18000000 384 MB
48 * KC705 0x38000000 896 MB
53 #if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000
[all …]
/openbmc/linux/drivers/net/ethernet/ibm/emac/
H A Dtah.h52 #define TAH_MR_CVR 0x80000000
53 #define TAH_MR_SR 0x40000000
54 #define TAH_MR_ST_256 0x01000000
55 #define TAH_MR_ST_512 0x02000000
56 #define TAH_MR_ST_768 0x03000000
57 #define TAH_MR_ST_1024 0x04000000
58 #define TAH_MR_ST_1280 0x05000000
59 #define TAH_MR_ST_1536 0x06000000
60 #define TAH_MR_TFS_16KB 0x00000000
61 #define TAH_MR_TFS_2KB 0x00200000
[all …]
/openbmc/u-boot/board/samtec/vining_fpga/qts/
H A Diocsr_config.h15 0x00000000,
16 0x00000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x00060180,
22 0x18060000,
23 0x18000000,
24 0x00018060,
[all …]
/openbmc/u-boot/board/terasic/sockit/qts/
H A Diocsr_config.h15 0x00000000,
16 0x00000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x00060180,
22 0x18060000,
23 0x18000000,
24 0x00018060,
[all …]
/openbmc/u-boot/board/sr1500/qts/
H A Diocsr_config.h15 0x00100000,
16 0x40000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x000E0180,
22 0x18060000,
23 0x18000000,
24 0x00018060,
[all …]
/openbmc/u-boot/board/terasic/de1-soc/qts/
H A Diocsr_config.h15 0x00000000,
16 0x00000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x00060180,
22 0x18060000,
23 0x18000000,
24 0x00018060,
[all …]
/openbmc/u-boot/board/freescale/mx53evk/
H A Dimximage.cfg33 DATA 4 0x53fa8554 0x00200000
34 DATA 4 0x53fa8560 0x00200000
35 DATA 4 0x53fa8594 0x00200000
36 DATA 4 0x53fa8584 0x00200000
37 DATA 4 0x53fa8558 0x00200040
38 DATA 4 0x53fa8568 0x00200040
39 DATA 4 0x53fa8590 0x00200040
40 DATA 4 0x53fa857c 0x00200040
41 DATA 4 0x53fa8564 0x00200040
42 DATA 4 0x53fa8580 0x00200040
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dreg_8xx.h29 #define SPRN_EID 81 /* External interrupt disable (EE=0, RI=1) */
30 #define SPRN_NRI 82 /* Non recoverable interrupt (EE=0, RI=0) */
38 #define LCTRL1_CTE_GT 0xc0000000
39 #define LCTRL1_CTF_LT 0x14000000
40 #define LCTRL1_CRWE_RW 0x00000000
41 #define LCTRL1_CRWE_RO 0x00040000
42 #define LCTRL1_CRWE_WO 0x000c0000
43 #define LCTRL1_CRWF_RW 0x00000000
44 #define LCTRL1_CRWF_RO 0x00010000
45 #define LCTRL1_CRWF_WO 0x00030000
[all …]
/openbmc/linux/arch/mips/boot/dts/brcm/
H A Dbcm3384_viper.dtsi7 memory@0 {
11 reg = <0x06000000 0x02000000>,
12 <0x0e000000 0x02000000>;
17 #size-cells = <0>;
22 cpu@0 {
25 reg = <0>;
30 #address-cells = <0>;
40 #clock-cells = <0>;
59 reg = <0x14e00048 0x4 0x14e0004c 0x4>,
60 <0x14e00350 0x4 0x14e00354 0x4>;
[all …]
/openbmc/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2800usb.h25 #define FIRMWARE_IMAGE_BASE 0x3000
39 * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
41 * 0:MGMT, 1:HCCA 2:EDCA
46 #define TXINFO_W0_USB_DMA_TX_PKT_LEN FIELD32(0x0000ffff)
47 #define TXINFO_W0_WIV FIELD32(0x01000000)
48 #define TXINFO_W0_QSEL FIELD32(0x06000000)
49 #define TXINFO_W0_SW_USE_LAST_ROUND FIELD32(0x08000000)
50 #define TXINFO_W0_USB_DMA_NEXT_VALID FIELD32(0x40000000)
51 #define TXINFO_W0_USB_DMA_TX_BURST FIELD32(0x80000000)
58 * Word 0
[all …]

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