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/openbmc/u-boot/arch/arm/dts/
H A Drk3399-sdram-ddr3-1866.dtsi8 0x1
9 0xa
10 0x3
11 0x2
12 0x1
13 0x0
14 0xf
15 0xf
17 0x80181219
18 0x17050a03
[all …]
H A Drk3399-sdram-ddr3-1333.dtsi8 0x1
9 0xa
10 0x3
11 0x2
12 0x1
13 0x0
14 0xf
15 0xf
17 0x80120e12
18 0x11030802
[all …]
H A Drk3399-sdram-ddr3-1600.dtsi8 0x1
9 0xa
10 0x3
11 0x2
12 0x1
13 0x0
14 0xf
15 0xf
17 0x80151015
18 0x14040902
[all …]
H A Drk3399-sdram-lpddr3-4GB-1600.dtsi8 0x2
9 0xa
10 0x3
11 0x2
12 0x2
13 0x0
14 0xf
15 0xf
17 0x1d191519
18 0x14040808
[all …]
H A Drk3399-sdram-lpddr3-2GB-1600.dtsi9 0x1
10 0xa
11 0x3
12 0x2
13 0x2
14 0x0
15 0xf
16 0xf
18 0x1d191519
19 0x14040808
[all …]
H A Drk3399-sdram-lpddr3-samsung-4GB-1866.dtsi8 0x2
9 0xa
10 0x3
11 0x2
12 0x2
13 0x0
14 0xf
15 0xf
18 0x801d181e
19 0x17050a08
[all …]
/openbmc/u-boot/board/freescale/mx7dsabresd/
H A Dimximage.cfg43 DATA 4 0x30340004 0x4F400005
45 DATA 4 0x30391000 0x00000002
46 DATA 4 0x307a0000 0x01040001
47 DATA 4 0x307a01a0 0x80400003
48 DATA 4 0x307a01a4 0x00100020
49 DATA 4 0x307a01a8 0x80100004
50 DATA 4 0x307a0064 0x00400046
51 DATA 4 0x307a0490 0x00000001
52 DATA 4 0x307a00d0 0x00020083
53 DATA 4 0x307a00d4 0x00690000
[all …]
/openbmc/u-boot/board/technexion/pico-imx7d/
H A Dspl.c20 return 0; in spl_start_uboot()
25 .mstr = 0x01040001,
26 .rfshtmg = 0x00400046,
27 .init1 = 0x00690000,
28 .init0 = 0x00020083,
29 .init3 = 0x09300004,
30 .init4 = 0x04080000,
31 .init5 = 0x00100004,
32 .rankctl = 0x0000033F,
33 .dramtmg0 = 0x09081109,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,sdx55-pas.yaml80 reg = <0x04080000 0x4040>;
86 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
99 qcom,smem-states = <&modem_smp2p_out 0>;
H A Dqcom,sc7180-pas.yaml103 reg = <0x04080000 0x4040>;
109 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
125 qcom,smem-states = <&modem_smp2p_out 0>;
H A Dqcom,sc7180-mss-pil.yaml198 reg = <0x04080000 0x10000>, <0x04180000 0x48>;
201 iommus = <&apps_smmu 0x461 0x0>, <&apps_smmu 0x444 0x3>;
204 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
231 qcom,smem-states = <&modem_smp2p_out 0>;
238 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
239 qcom,spare-regs = <&tcsr_regs 0xb3e4>;
H A Dqcom,sc7280-mss-pil.yaml216 reg = <0x04080000 0x10000>, <0x04180000 0x48>;
219 iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;
221 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
224 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
248 qcom,smem-states = <&modem_smp2p_out 0>;
255 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>;
256 qcom,ext-regs = <&tcsr 0x10000 0x10004>, <&tcsr_mutex 0x26004 0x26008>;
257 qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>;
H A Dqcom,msm8916-mss-pil.yaml253 reg = <0x04080000 0x100>, <0x04020000 0x40>;
257 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
263 qcom,smem-states = <&hexagon_smp2p_out 0>;
265 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
277 resets = <&scm 0>;
285 qcom,smd-edge = <0>;
H A Dqcom,msm8996-mss-pil.yaml348 reg = <0x04080000 0x408>, <0x04180000 0x48>;
352 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
382 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
386 qcom,smem-states = <&modem_smp2p_out 0>;
/openbmc/u-boot/board/compulab/cl-som-imx7/
H A Dspl.c22 USDHC1_BASE_ADDR, 0, 4};
38 .init1 = 0x00690000,
39 .init0 = 0x00020083,
40 .init3 = 0x09300004,
41 .init4 = 0x04080000,
42 .init5 = 0x00100004,
43 .rankctl = 0x0000033F,
44 .dramtmg1 = 0x0007020E,
45 .dramtmg2 = 0x03040407,
46 .dramtmg3 = 0x00002006,
[all …]
/openbmc/u-boot/arch/arm/mach-keystone/include/mach/
H A Dhardware.h26 #define KS2_DDRPHY_PIR_OFFSET 0x04
27 #define KS2_DDRPHY_PGCR0_OFFSET 0x08
28 #define KS2_DDRPHY_PGCR1_OFFSET 0x0C
29 #define KS2_DDRPHY_PGSR0_OFFSET 0x10
30 #define KS2_DDRPHY_PGSR1_OFFSET 0x14
31 #define KS2_DDRPHY_PLLCR_OFFSET 0x18
32 #define KS2_DDRPHY_PTR0_OFFSET 0x1C
33 #define KS2_DDRPHY_PTR1_OFFSET 0x20
34 #define KS2_DDRPHY_PTR2_OFFSET 0x24
35 #define KS2_DDRPHY_PTR3_OFFSET 0x28
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsc7180-idp.dts50 reg = <0x0 0x94600000 0x0 0x800000>;
56 reg = <0x0 0x80b00000 0x0 0x100000>;
61 reg = <0x0 0x86000000 0x0 0x8c00000>;
66 reg = <0x0 0x8ec00000 0x0 0x500000>;
71 reg = <0 0x8f600000 0 0x500000>;
76 reg = <0x0 0x94100000 0x0 0x200000>;
81 reg = <0x0 0x94400000 0x0 0x200000>;
86 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
87 size = <0x0 0x4000>;
94 regulators-0 {
[all …]
H A Dsc7180-trogdor.dtsi24 polling-delay-passive = <0>;
25 polling-delay = <0>;
27 thermal-sensors = <&pm6150_adc_tm 0>;
56 reg = <0x0 0x94600000 0x0 0x800000>;
62 reg = <0x0 0x80b00000 0x0 0x100000>;
67 reg = <0x0 0x86000000 0x0 0x2000000>;
72 reg = <0 0x8f600000 0 0x500000>;
77 reg = <0x0 0x94100000 0x0 0x200000>;
82 reg = <0x0 0x94400000 0x0 0x200000>;
87 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
[all …]
H A Dmsm8953.dtsi25 #clock-cells = <0>;
31 #clock-cells = <0>;
39 #size-cells = <0>;
41 CPU0: cpu@0 {
44 reg = <0x0>;
54 reg = <0x1>;
64 reg = <0x2>;
74 reg = <0x3>;
84 reg = <0x100>;
94 reg = <0x101>;
[all …]
H A Dmsm8939.dtsi29 #clock-cells = <0>;
35 #clock-cells = <0>;
42 #size-cells = <0>;
48 reg = <0x100>;
66 reg = <0x101>;
79 reg = <0x102>;
92 reg = <0x103>;
101 CPU4: cpu@0 {
105 reg = <0x0>;
123 reg = <0x1>;
[all …]
H A Dmsm8916.dtsi26 reg = <0 0x80000000 0 0>;
35 reg = <0x0 0x86000000 0x0 0x300000>;
41 reg = <0x0 0x86300000 0x0 0x100000>;
49 reg = <0x0 0x86400000 0x0 0x100000>;
54 reg = <0x0 0x86500000 0x0 0x180000>;
59 reg = <0x0 0x86680000 0x0 0x80000>;
65 reg = <0x0 0x86700000 0x0 0xe0000>;
72 reg = <0x0 0x867e0000 0x0 0x20000>;
77 reg = <0x0 0x86800000 0x0 0x2b00000>;
82 reg = <0x0 0x89300000 0x0 0x600000>;
[all …]
H A Dsm6350.dtsi31 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
81 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-sdx65.dtsi20 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
25 reg = <0 0>;
33 #clock-cells = <0>;
40 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #size-cells = <0>;
54 cpu0: cpu@0 {
57 reg = <0x0>;
115 reg = <0x8fcad000 0x40000>;
120 reg = <0x8fcfd000 0x1000>;
[all …]
H A Dqcom-sdx55.dtsi20 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
25 reg = <0 0>;
31 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #clock-cells = <0>;
51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x0>;
108 reg = <0x8fc00000 0x80000>;
113 reg = <0x8fc80000 0x40000>;
[all …]
/openbmc/linux/drivers/scsi/
H A Dpmcraid.h33 #define PMCRAID_FW_VERSION_1 0x002
38 /* Bit definitions as per firmware, bit position [0][1][2].....[31] */
44 #define PCI_VENDOR_ID_PMC 0x11F8
45 #define PCI_DEVICE_ID_PMC_MAXRAID 0x5220
92 #define PMCRAID_IOA_BUS_ID 0xfe
93 #define PMCRAID_IOA_TARGET_ID 0xff
94 #define PMCRAID_IOA_LUN_ID 0xff
95 #define PMCRAID_VSET_BUS_ID 0x1
96 #define PMCRAID_VSET_LUN_ID 0x0
97 #define PMCRAID_PHYS_BUS_ID 0x0
[all …]

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