Lines Matching +full:0 +full:x04080000
26 #define KS2_DDRPHY_PIR_OFFSET 0x04
27 #define KS2_DDRPHY_PGCR0_OFFSET 0x08
28 #define KS2_DDRPHY_PGCR1_OFFSET 0x0C
29 #define KS2_DDRPHY_PGSR0_OFFSET 0x10
30 #define KS2_DDRPHY_PGSR1_OFFSET 0x14
31 #define KS2_DDRPHY_PLLCR_OFFSET 0x18
32 #define KS2_DDRPHY_PTR0_OFFSET 0x1C
33 #define KS2_DDRPHY_PTR1_OFFSET 0x20
34 #define KS2_DDRPHY_PTR2_OFFSET 0x24
35 #define KS2_DDRPHY_PTR3_OFFSET 0x28
36 #define KS2_DDRPHY_PTR4_OFFSET 0x2C
37 #define KS2_DDRPHY_DCR_OFFSET 0x44
39 #define KS2_DDRPHY_DTPR0_OFFSET 0x48
40 #define KS2_DDRPHY_DTPR1_OFFSET 0x4C
41 #define KS2_DDRPHY_DTPR2_OFFSET 0x50
43 #define KS2_DDRPHY_MR0_OFFSET 0x54
44 #define KS2_DDRPHY_MR1_OFFSET 0x58
45 #define KS2_DDRPHY_MR2_OFFSET 0x5C
46 #define KS2_DDRPHY_DTCR_OFFSET 0x68
47 #define KS2_DDRPHY_PGCR2_OFFSET 0x8C
49 #define KS2_DDRPHY_ZQ0CR1_OFFSET 0x184
50 #define KS2_DDRPHY_ZQ1CR1_OFFSET 0x194
51 #define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4
52 #define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4
54 #define KS2_DDRPHY_DATX8_2_OFFSET 0x240
55 #define KS2_DDRPHY_DATX8_3_OFFSET 0x280
56 #define KS2_DDRPHY_DATX8_4_OFFSET 0x2C0
57 #define KS2_DDRPHY_DATX8_5_OFFSET 0x300
58 #define KS2_DDRPHY_DATX8_6_OFFSET 0x340
59 #define KS2_DDRPHY_DATX8_7_OFFSET 0x380
60 #define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0
62 #define IODDRM_MASK 0x00000180
63 #define ZCKSEL_MASK 0x01800000
64 #define CL_MASK 0x00000072
65 #define WR_MASK 0x00000E00
66 #define BL_MASK 0x00000003
67 #define RRMODE_MASK 0x00040000
68 #define UDIMM_MASK 0x20000000
69 #define BYTEMASK_MASK 0x0003FC00
70 #define MPRDQ_MASK 0x00000080
71 #define PDQ_MASK 0x00000070
72 #define NOSRA_MASK 0x08000000
73 #define ECC_MASK 0x00000001
74 #define DXEN_MASK 0x00000001
77 #define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000
78 #define KS2_DDR3A_EMIF_DATA_BASE 0x80000000
79 #define KS2_DDR3A_DDRPHYC 0x02329000
82 #define KS2_DDR3_MIDR_OFFSET 0x00
83 #define KS2_DDR3_STATUS_OFFSET 0x04
84 #define KS2_DDR3_SDCFG_OFFSET 0x08
85 #define KS2_DDR3_SDRFC_OFFSET 0x10
86 #define KS2_DDR3_SDTIM1_OFFSET 0x18
87 #define KS2_DDR3_SDTIM2_OFFSET 0x1C
88 #define KS2_DDR3_SDTIM3_OFFSET 0x20
89 #define KS2_DDR3_SDTIM4_OFFSET 0x28
90 #define KS2_DDR3_PMCTL_OFFSET 0x38
91 #define KS2_DDR3_ZQCFG_OFFSET 0xC8
93 #define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000
96 #define KS2_DDR3_ECC_INT_STATUS_OFFSET 0x0AC
97 #define KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET 0x0B4
98 #define KS2_DDR3_ECC_CTRL_OFFSET 0x110
99 #define KS2_DDR3_ECC_ADDR_RANGE1_OFFSET 0x114
100 #define KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET 0x130
101 #define KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET 0x13C
113 #define KS2_DDR3_ECC_ADDR_RNG_1_EN BIT(0)
120 #define KS2_EDMA0_BASE 0x02700000
123 #define KS2_EDMA_QCHMAP0 0x0200
124 #define KS2_EDMA_IPR 0x1068
125 #define KS2_EDMA_ICR 0x1070
126 #define KS2_EDMA_QEECR 0x1088
127 #define KS2_EDMA_QEESR 0x108c
128 #define KS2_EDMA_PARAM_1(x) (0x4020 + (4 * x))
140 #define KS2_CIC2_BASE 0x02608000
143 #define KS2_CIC_CTRL 0x04
144 #define KS2_CIC_HOST_CTRL 0x0C
145 #define KS2_CIC_GLOBAL_ENABLE 0x10
146 #define KS2_CIC_SYS_ENABLE_IDX_SET 0x28
147 #define KS2_CIC_HOST_ENABLE_IDX_SET 0x34
148 #define KS2_CIC_CHAN_MAP(n) (0x0400 + (n << 2))
150 #define KS2_UART0_BASE 0x02530c00
151 #define KS2_UART1_BASE 0x02531000
154 #define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
155 #define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
156 #define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
157 #define KS2_DEVCFG (KS2_DEVICE_STATE_CTRL_BASE + 0x14c)
158 #define KS2_ETHERNET_CFG (KS2_DEVICE_STATE_CTRL_BASE + 0xe20)
162 #define KS2_PSC_BASE 0x02350000
169 #define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
170 #define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
171 #define KS2_KICK0_MAGIC 0x83e70b13
172 #define KS2_KICK1_MAGIC 0x95a4f1e0
175 #define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
176 #define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
177 #define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
178 #define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
179 #define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
180 #define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
181 #define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
182 #define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
183 #define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
184 #define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
185 #define KS2_UARTPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x390)
186 #define KS2_UARTPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x394)
188 #define KS2_PLL_CNTRL_BASE 0x02310000
190 #define KS2_RSTCTRL_RSTYPE (KS2_PLL_CNTRL_BASE + 0xe4)
191 #define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8)
192 #define KS2_RSTCTRL_RSCFG (KS2_PLL_CNTRL_BASE + 0xec)
193 #define KS2_RSTCTRL_KEY 0x5a69
194 #define KS2_RSTCTRL_MASK 0xffff0000
195 #define KS2_RSTCTRL_SWRST 0xfffe0000
200 #define KS2_SPI0_BASE 0x21805400
201 #define KS2_SPI1_BASE 0x21805800
202 #define KS2_SPI2_BASE 0x21805c00
203 #define KS2_SPI3_BASE 0x21806000
205 #define KS2_SPI0_BASE 0x21000400
206 #define KS2_SPI1_BASE 0x21000600
207 #define KS2_SPI2_BASE 0x21000800
212 #define KS2_AEMIF_CNTRL_BASE 0x21000a00
216 #define DBG_LEAVE_DSPS_ON 0x1
219 #define KS2_MSMC_CTRL_BASE 0x0bc00000
220 #define KS2_MSMC_DATA_BASE 0x0c000000
223 #define KS2_MSMC_SEGMENT_C6X_0 0
269 #define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
270 #define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
271 #define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
275 #define KS2_QM_BASE_ADDRESS 0x040C0000
276 #define KS2_QM_CONF_BASE 0x04040000
277 #define KS2_QM_DESC_SETUP_BASE 0x04080000
278 #define KS2_QM_STATUS_RAM_BASE 0x0 /* K2G doesn't have it */
279 #define KS2_QM_INTD_CONF_BASE 0x0
280 #define KS2_QM_PDSP1_CMD_BASE 0x0
281 #define KS2_QM_PDSP1_CTRL_BASE 0x0
282 #define KS2_QM_PDSP1_IRAM_BASE 0x0
283 #define KS2_QM_MANAGER_QUEUES_BASE 0x040c0000
284 #define KS2_QM_MANAGER_Q_PROXY_BASE 0x04040200
285 #define KS2_QM_QUEUE_STATUS_BASE 0x04100000
286 #define KS2_QM_LINK_RAM_BASE 0x04020000
290 #define KS2_QM_BASE_ADDRESS 0x23a80000
291 #define KS2_QM_CONF_BASE 0x02a02000
292 #define KS2_QM_DESC_SETUP_BASE 0x02a03000
293 #define KS2_QM_STATUS_RAM_BASE 0x02a06000
294 #define KS2_QM_INTD_CONF_BASE 0x02a0c000
295 #define KS2_QM_PDSP1_CMD_BASE 0x02a20000
296 #define KS2_QM_PDSP1_CTRL_BASE 0x02a0f000
297 #define KS2_QM_PDSP1_IRAM_BASE 0x02a10000
298 #define KS2_QM_MANAGER_QUEUES_BASE 0x02a80000
299 #define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
300 #define KS2_QM_QUEUE_STATUS_BASE 0x02a40000
301 #define KS2_QM_LINK_RAM_BASE 0x00100000
307 #define KS2_USB_SS_BASE 0x02680000
308 #define KS2_USB_HOST_XHCI_BASE (KS2_USB_SS_BASE + 0x10000)
309 #define KS2_DEV_USB_PHY_BASE 0x02620738
310 #define KS2_USB_PHY_CFG_BASE 0x02630000
312 #define KS2_MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
315 #define KS2_SGMII_SERDES_BASE 0x0232a000
319 #define JTAGID_VARIANT_MASK (0xf << 28)
321 #define JTAGID_PART_NUM_MASK (0xffff << 12)
324 #define CPU_66AK2Hx 0xb981
325 #define CPU_66AK2Ex 0xb9a6
326 #define CPU_66AK2Lx 0xb9a7
327 #define CPU_66AK2Gx 0xbb06
330 #define CPU_66AK2G1x 0x08
334 #define DEVSPEED_DEVSPEED_MASK (0xfff << 16)
335 #define DEVSPEED_ARMSPEED_SHIFT 0
336 #define DEVSPEED_ARMSPEED_MASK 0xfff