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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx93-pinfunc.h13 #define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0
14 #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0
15 #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0
16 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
17 #define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0
18 #define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0
19 #define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0
20 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
21 #define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0
22 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra210-pinmux.yaml122 reg = <0x700008d4 0x02a8>, /* Pad control registers */
123 <0x70003000 0x1000>; /* Mux registers */
126 pinctrl-0 = <&state_boot>;
/openbmc/u-boot/arch/arm/dts/
H A Dimx7d-pinfunc.h18 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
24 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
25 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
26 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
27 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
H A Dimx6sx-pinfunc.h17 #define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
18 #define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
19 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
20 #define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
21 #define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
22 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
23 #define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
24 #define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
25 #define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
26 #define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
[all …]
H A Dimx7ulp-pinfunc.h26 #define ULP1_PAD_PTA0_LLWU0_P0__CMP0_IN2A 0x0000 0x0000 0x0 0x0
27 #define ULP1_PAD_PTA0_LLWU0_P0__PTA0 0x0000 0x0000 0x1 0x0
28 #define ULP1_PAD_PTA0_LLWU0_P0__LLWU0_P0 0x0000 0x0000 0xd 0x0
29 #define ULP1_PAD_PTA0_LLWU0_P0__LPSPI0_PCS1 0x0000 0xd104 0x3 0x2
30 #define ULP1_PAD_PTA0_LLWU0_P0__LPUART0_CTS_B 0x0000 0xd1f8 0x4 0x2
31 #define ULP1_PAD_PTA0_LLWU0_P0__LPI2C0_SCL 0x0000 0xd17c 0x5 0x2
32 #define ULP1_PAD_PTA0_LLWU0_P0__TPM0_CLKIN 0x0000 0xd1a8 0x6 0x2
33 #define ULP1_PAD_PTA0_LLWU0_P0__I2S0_RX_BCLK 0x0000 0x01b8 0x7 0x2
34 #define ULP1_PAD_PTA1__CMP0_IN2B 0x0004 0x0000 0x0 0x0
35 #define ULP1_PAD_PTA1__PTA1 0x0004 0x0000 0x1 0x0
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
H A Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
H A Dimx6sx-pinfunc.h13 #define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
14 #define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
15 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
16 #define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
17 #define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
18 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
19 #define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
20 #define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
21 #define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
22 #define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
[all …]
/openbmc/linux/drivers/net/can/spi/mcp251xfd/
H A Dmcp251xfd-crc16.c24 0x0000, 0x8005, 0x800f, 0x000a, 0x801b, 0x001e, 0x0014, 0x8011,
25 0x8033, 0x0036, 0x003c, 0x8039, 0x0028, 0x802d, 0x8027, 0x0022,
26 0x8063, 0x0066, 0x006c, 0x8069, 0x0078, 0x807d, 0x8077, 0x0072,
27 0x0050, 0x8055, 0x805f, 0x005a, 0x804b, 0x004e, 0x0044, 0x8041,
28 0x80c3, 0x00c6, 0x00cc, 0x80c9, 0x00d8, 0x80dd, 0x80d7, 0x00d2,
29 0x00f0, 0x80f5, 0x80ff, 0x00fa, 0x80eb, 0x00ee, 0x00e4, 0x80e1,
30 0x00a0, 0x80a5, 0x80af, 0x00aa, 0x80bb, 0x00be, 0x00b4, 0x80b1,
31 0x8093, 0x0096, 0x009c, 0x8099, 0x0088, 0x808d, 0x8087, 0x0082,
32 0x8183, 0x0186, 0x018c, 0x8189, 0x0198, 0x819d, 0x8197, 0x0192,
33 0x01b0, 0x81b5, 0x81bf, 0x01ba, 0x81ab, 0x01ae, 0x01a4, 0x81a1,
[all …]
/openbmc/openbmc/meta-fii/meta-kudo/recipes-kudo/kudo-fw-utility/kudo-fw/
H A Dkudo-fw.sh14 i2cset -y -f -a ${I2C_BMC_CPLD[0]} 0x${I2C_BMC_CPLD[1]} 0x10 0x01
32 if [ "$(flashcp -v $1 /dev/${BIOS_MTD})" -ne 0 ]; then
42 i2cset -y -f -a ${I2C_BMC_CPLD[0]} 0x${I2C_BMC_CPLD[1]} 0x10 0x00
45 if [ "$(nvparm -s 0x1 -o 0x114090)" -ne 0 ]; then
51 if [ "$(nvparm -s 0x1 -o 0x02A8)" -ne 0 ]; then
57 if [ "$(nvparm -s 0x0 -o 0x5F0638)" -ne 0 ]; then
71 return 0
75 # BMC_JTAG_MUX_1 0:BMC 1:MB
76 set_gpio_ctrl MB_JTAG_MUX_SEL 0
77 if [ "$(loadsvf -d /dev/jtag0 -s $1 -m 0)" -ne 0 ]; then
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_1_0_d.h26 #define ixCLIENT0_BM 0x0220
27 #define ixCLIENT0_CD0 0x0210
28 #define ixCLIENT0_CD1 0x0214
29 #define ixCLIENT0_CD2 0x0218
30 #define ixCLIENT0_CD3 0x021C
31 #define ixCLIENT0_CK0 0x0200
32 #define ixCLIENT0_CK1 0x0204
33 #define ixCLIENT0_CK2 0x0208
34 #define ixCLIENT0_CK3 0x020C
35 #define ixCLIENT0_K0 0x01F0
[all …]
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8183-apmixedsys.c19 .set_ofs = 0x20,
20 .clr_ofs = 0x20,
21 .sta_ofs = 0x20,
29 GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0)
93 { .div = 0, .freq = MT8183_PLL_FMAX },
102 { .div = 0, .freq = MT8183_PLL_FMAX },
111 PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0,
112 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0,
113 0x0204, 0, 0, armpll_div_table),
114 PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0,
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-vf610/
H A Diomux-vf610.h46 VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
47 VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
48 VF610_PAD_PTA7__GPIO_134 = IOMUX_PAD(0x0218, 0x0218, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
49 VF610_PAD_PTA17__GPIO_7 = IOMUX_PAD(0x001c, 0x001c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
50 VF610_PAD_PTA20__GPIO_10 = IOMUX_PAD(0x0028, 0x0028, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
51 VF610_PAD_PTA21__GPIO_11 = IOMUX_PAD(0x002c, 0x002c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
52 VF610_PAD_PTA30__GPIO_20 = IOMUX_PAD(0x0050, 0x0050, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
53 VF610_PAD_PTA31__GPIO_21 = IOMUX_PAD(0x0054, 0x0054, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
54 VF610_PAD_PTB0__GPIO_22 = IOMUX_PAD(0x0058, 0x0058, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
55 VF610_PAD_PTB1__GPIO_23 = IOMUX_PAD(0x005C, 0x005C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dimx8mq_pins.h12 IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0),
13 IMX8MQ_PAD_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0),
14 IMX8MQ_PAD_GPIO1_IO00__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0),
15 IMX8MQ_PAD_GPIO1_IO00__CCM_EXT_CLK1 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0),
16 IMX8MQ_PAD_GPIO1_IO00__JTAG_FAIL = IOMUX_PAD(0x0290, 0x0028, 7, 0x0000, 0, 0),
18 IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1 = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0),
19 IMX8MQ_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0),
20 IMX8MQ_PAD_GPIO1_IO01__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0),
21 IMX8MQ_PAD_GPIO1_IO01__CCM_EXT_CLK2 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0),
22 IMX8MQ_PAD_GPIO1_IO01__JTAG_ACTIVE = IOMUX_PAD(0x0294, 0x002C, 7, 0x0000, 0, 0),
[all …]
/openbmc/linux/include/linux/mfd/mt6397/
H A Dregisters.h11 #define MT6397_CID 0x0100
12 #define MT6397_TOP_CKPDN 0x0102
13 #define MT6397_TOP_CKPDN_SET 0x0104
14 #define MT6397_TOP_CKPDN_CLR 0x0106
15 #define MT6397_TOP_CKPDN2 0x0108
16 #define MT6397_TOP_CKPDN2_SET 0x010A
17 #define MT6397_TOP_CKPDN2_CLR 0x010C
18 #define MT6397_TOP_GPIO_CKPDN 0x010E
19 #define MT6397_TOP_RST_CON 0x0114
20 #define MT6397_WRP_CKPDN 0x011A
[all …]
/openbmc/linux/drivers/media/platform/ti/vpe/
H A Dsc_coeff.h17 HS_UP_SCALE = 0,
31 0x001F, 0x1F90, 0x00D2, 0x06FE, 0x00D2, 0x1F90, 0x001F,
32 0x001C, 0x1F9E, 0x009F, 0x06FB, 0x0108, 0x1F82, 0x0022,
33 0x0019, 0x1FAC, 0x006F, 0x06F3, 0x0140, 0x1F74, 0x0025,
34 0x0016, 0x1FB9, 0x0041, 0x06E7, 0x017B, 0x1F66, 0x0028,
35 0x0013, 0x1FC6, 0x0017, 0x06D6, 0x01B7, 0x1F58, 0x002B,
36 0x0010, 0x1FD3, 0x1FEF, 0x06C0, 0x01F6, 0x1F4B, 0x002D,
37 0x000E, 0x1FDF, 0x1FCB, 0x06A5, 0x0235, 0x1F3F, 0x002F,
38 0x000B, 0x1FEA, 0x1FAA, 0x0686, 0x0277, 0x1F33, 0x0031,
39 0x0009, 0x1FF5, 0x1F8C, 0x0663, 0x02B8, 0x1F28, 0x0033,
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/mp/
H A Dmp_13_0_8_offset.h31 // base address: 0x0
32 …MP0_SMN_C2PMSG_32 0x0060
33 …e regMP0_SMN_C2PMSG_32_BASE_IDX 0
34 …MP0_SMN_C2PMSG_33 0x0061
35 …e regMP0_SMN_C2PMSG_33_BASE_IDX 0
36 …MP0_SMN_C2PMSG_34 0x0062
37 …e regMP0_SMN_C2PMSG_34_BASE_IDX 0
38 …MP0_SMN_C2PMSG_35 0x0063
39 …e regMP0_SMN_C2PMSG_35_BASE_IDX 0
40 …MP0_SMN_C2PMSG_36 0x0064
[all …]
H A Dmp_11_5_0_offset.h27 // base address: 0x0
28 …MP0_SMN_C2PMSG_32 0x0060
29 …ne mmMP0_SMN_C2PMSG_32_BASE_IDX 0
30 …MP0_SMN_C2PMSG_33 0x0061
31 …ne mmMP0_SMN_C2PMSG_33_BASE_IDX 0
32 …MP0_SMN_C2PMSG_34 0x0062
33 …ne mmMP0_SMN_C2PMSG_34_BASE_IDX 0
34 …MP0_SMN_C2PMSG_35 0x0063
35 …ne mmMP0_SMN_C2PMSG_35_BASE_IDX 0
36 …MP0_SMN_C2PMSG_36 0x0064
[all …]
H A Dmp_13_0_0_offset.h28 // base address: 0x0
29 …MP0_SMN_C2PMSG_32 0x0060
30 …e regMP0_SMN_C2PMSG_32_BASE_IDX 0
31 …MP0_SMN_C2PMSG_33 0x0061
32 …e regMP0_SMN_C2PMSG_33_BASE_IDX 0
33 …MP0_SMN_C2PMSG_34 0x0062
34 …e regMP0_SMN_C2PMSG_34_BASE_IDX 0
35 …MP0_SMN_C2PMSG_35 0x0063
36 …e regMP0_SMN_C2PMSG_35_BASE_IDX 0
37 …MP0_SMN_C2PMSG_36 0x0064
[all …]
H A Dmp_13_0_6_offset.h29 // base address: 0x0
30 …MP0_SMN_C2PMSG_32 0x0060
31 …e regMP0_SMN_C2PMSG_32_BASE_IDX 0
32 …MP0_SMN_C2PMSG_33 0x0061
33 …e regMP0_SMN_C2PMSG_33_BASE_IDX 0
34 …MP0_SMN_C2PMSG_34 0x0062
35 …e regMP0_SMN_C2PMSG_34_BASE_IDX 0
36 …MP0_SMN_C2PMSG_35 0x0063
37 …e regMP0_SMN_C2PMSG_35_BASE_IDX 0
38 …MP0_SMN_C2PMSG_36 0x0064
[all …]
H A Dmp_13_0_5_offset.h30 // base address: 0x0
31 …MP0_SMN_C2PMSG_32 0x0060
32 …e regMP0_SMN_C2PMSG_32_BASE_IDX 0
33 …MP0_SMN_C2PMSG_33 0x0061
34 …e regMP0_SMN_C2PMSG_33_BASE_IDX 0
35 …MP0_SMN_C2PMSG_34 0x0062
36 …e regMP0_SMN_C2PMSG_34_BASE_IDX 0
37 …MP0_SMN_C2PMSG_35 0x0063
38 …e regMP0_SMN_C2PMSG_35_BASE_IDX 0
39 …MP0_SMN_C2PMSG_36 0x0064
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am642-phyboard-electra-rdk.dts43 pinctrl-0 = <&can_tc1_pins_default>;
44 #phy-cells = <0>;
52 pinctrl-0 = <&can_tc2_pins_default>;
53 #phy-cells = <0>;
62 pinctrl-0 = <&gpio_keys_pins_default>;
80 pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>;
111 AM64X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (P16) GPMC0_ADVn_ALE.GPIO0_32 */
117 AM64X_IOPAD(0x0090, PIN_OUTPUT, 7) /* (P17) GPMC0_BE0n_CLE.GPIO0_35 */
123 AM64X_IOPAD(0x0044, PIN_INPUT, 7) /* (T18) GPMC0_AD2.GPIO0_17 */
124 AM64X_IOPAD(0x0054, PIN_INPUT, 7) /* (V20) GPMC0_AD6.GPIO0_21 */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx7/
H A Dmx7d_pins.h12 …0__GPIO1_IO0 = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 0, 0x0000, …
13 MX7D_PAD_GPIO1_IO00__PWM4_OUT = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0),
14 …0__WDOG1_WDOG_B = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 3, 0x0000, …
16 …1__GPIO1_IO1 = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 0, 0x0000, …
17 …1__PWM1_OUT = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 1, 0x0000, …
18 …1__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 2, 0x0000, …
19 …MX7D_PAD_GPIO1_IO01__SAI1_MCLK = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0…
21 …2__GPIO1_IO2 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 0, 0x0000, …
22 …2__PWM2_OUT = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 1, 0x0000, …
23 …2__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 2, 0x0564, …
[all …]
/openbmc/u-boot/drivers/power/domain/
H A Dmtk-power-domain.c20 #define SPM_EN (0xb16 << 16 | 0x1)
21 #define SPM_VDE_PWR_CON 0x0210
22 #define SPM_MFG_PWR_CON 0x0214
23 #define SPM_ISP_PWR_CON 0x0238
24 #define SPM_DIS_PWR_CON 0x023c
25 #define SPM_CONN_PWR_CON 0x0280
26 #define SPM_BDP_PWR_CON 0x029c
27 #define SPM_ETH_PWR_CON 0x02a0
28 #define SPM_HIF_PWR_CON 0x02a4
29 #define SPM_IFR_MSC_PWR_CON 0x02a8
[all …]
/openbmc/linux/drivers/gpu/drm/rockchip/
H A Drockchip_vop_reg.h11 #define RK3288_REG_CFG_DONE 0x0000
12 #define RK3288_VERSION_INFO 0x0004
13 #define RK3288_SYS_CTRL 0x0008
14 #define RK3288_SYS_CTRL1 0x000c
15 #define RK3288_DSP_CTRL0 0x0010
16 #define RK3288_DSP_CTRL1 0x0014
17 #define RK3288_DSP_BG 0x0018
18 #define RK3288_MCU_CTRL 0x001c
19 #define RK3288_INTR_CTRL0 0x0020
20 #define RK3288_INTR_CTRL1 0x0024
[all …]

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