Searched +full:0 +full:x02184400 (Results 1 – 7 of 7) sorted by relevance
116 AHBBRST at SBUSCFG, the range is from 0x0 to 0x7. This property is121 minimum: 0x0122 maximum: 0x7130 is set to 0, if this property is missing the reset default of the133 minimum: 0x0134 maximum: 0x20142 is set to 0, if this property is missing the reset default of the145 minimum: 0x0146 maximum: 0x20154 required, empty <0> phandle should be specified.[all …]
24 memory { device_type = "memory"; reg = <0 0>; };48 #size-cells = <0>;50 cpu@0 {53 reg = <0x0>;83 reg = <0x00a01000 0x1000>,84 <0x00a00100 0x100>;90 #size-cells = <0>;94 #clock-cells = <0>;100 #clock-cells = <0>;114 reg = <0x00900000 0x20000>;[all …]
56 #clock-cells = <0>;62 #clock-cells = <0>;63 clock-frequency = <0>;68 #clock-cells = <0>;76 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;84 #size-cells = <0>;89 lvds-channel@0 {91 #size-cells = <0>;92 reg = <0>;95 port@0 {[all …]
56 #size-cells = <0>;58 cpu0: cpu@0 {61 reg = <0>;94 reg = <0x00a01000 0x1000>,95 <0x00a00100 0x100>;101 #size-cells = <0>;103 ckil: clock@0 {105 reg = <0>;106 #clock-cells = <0>;114 #clock-cells = <0>;[all …]
51 #size-cells = <0>;53 cpu0: cpu@0 {56 reg = <0x0>;86 #clock-cells = <0>;92 #clock-cells = <0>;100 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;105 #phy-cells = <0>;117 reg = <0x00900000 0x20000>;118 ranges = <0 0x00900000 0x20000>;128 reg = <0x00a01000 0x1000>,[all …]
59 #clock-cells = <0>;65 #clock-cells = <0>;66 clock-frequency = <0>;71 #clock-cells = <0>;78 #size-cells = <0>;83 lvds-channel@0 {85 #size-cells = <0>;86 reg = <0>;89 port@0 {90 reg = <0>;[all …]
61 #size-cells = <0>;63 cpu0: cpu@0 {66 reg = <0>;100 #clock-cells = <0>;107 #clock-cells = <0>;114 #clock-cells = <0>;115 clock-frequency = <0>;121 #clock-cells = <0>;122 clock-frequency = <0>;128 #clock-cells = <0>;[all …]