Lines Matching +full:0 +full:x02184400

116       AHBBRST at SBUSCFG, the range is from 0x0 to 0x7. This property is
121     minimum: 0x0
122     maximum: 0x7
130       is set to 0, if this property is missing the reset default of the
133     minimum: 0x0
134     maximum: 0x20
142       is set to 0, if this property is missing the reset default of the
145     minimum: 0x0
146     maximum: 0x20
154       required, empty <0> phandle should be specified.
169       will be 0x7f; if not, the value will be 0x0, this is the default
173       at RTL is 0, so this property only affects siTD.
191       It's expected that a mux state of 0 indicates device mode and a mux
220   pinctrl-0:
285       pins after a J-to-K or K-to-J transition. The range is from 0x0 to
286       0x3, the default value is 0x1. Details can refer to TXPREEMPAMPTUNE0
289     minimum: 0x0
290     maximum: 0x3
295       level voltage. The range is from 0x0 to 0xf, the default value is
296       0x3. Details can refer to TXVREFTUNE0 bits of USBNC_n_PHY_CFG1.
298     minimum: 0x0
299     maximum: 0xf
306       to design default time. (0:-10%; 1:design default; 2:+15%; 3:+20%)
309     minimum: 0
347       "^phy(-[0-9])?$":
423         reg = <0xf7ed0000 0x10000>;
429         itc-setting = <0x4>; /* 4 micro-frames */
431         ahb-burst-config = <0x0>;
432         tx-burst-size-dword = <0x10>; /* 64 bytes */
433         rx-burst-size-dword = <0x10>;
434         extcon = <0>, <&usb_id>;
447         reg = <0x02184400 0x200>;
448         interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
454         ahb-burst-config = <0x0>;
455         tx-burst-size-dword = <0x10>;
456         rx-burst-size-dword = <0x10>;
458         pinctrl-0 = <&pinctrl_usbh2_idle>;
461         #size-cells = <0>;