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/openbmc/u-boot/board/altera/cyclone5-socdk/qts/
H A Diocsr_config.h15 0x00000000,
16 0x00000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x00020080,
22 0x08020000,
23 0x08000000,
24 0x00018020,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,kpss-acc-v1.yaml47 const: 0
65 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
69 #clock-cells = <0>;
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8960.dtsi20 #size-cells = <0>;
21 interrupts = <GIC_PPI 14 0x304>;
23 cpu@0 {
27 reg = <0>;
52 reg = <0x0 0x0>;
57 interrupts = <GIC_PPI 10 0x304>;
64 #clock-cells = <0>;
71 #clock-cells = <0>;
78 #clock-cells = <0>;
103 reg = <0x02000000 0x1000>,
[all …]
H A Dqcom-apq8064.dtsi25 reg = <0x80000000 0x200000>;
30 reg = <0x8f000000 0x700000>;
37 #size-cells = <0>;
39 CPU0: cpu@0 {
43 reg = <0>;
100 memory@0 {
102 reg = <0x0 0x0>;
111 coefficients = <1199 0>;
132 coefficients = <1132 0>;
153 coefficients = <1199 0>;
[all …]
H A Dqcom-ipq8064.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
29 reg = <0>;
54 polling-delay-passive = <0>;
55 polling-delay = <0>;
56 thermal-sensors = <&tsens 0>;
74 polling-delay-passive = <0>;
75 polling-delay = <0>;
94 polling-delay-passive = <0>;
95 polling-delay = <0>;
[all …]
/openbmc/qemu/include/hw/arm/
H A Dfsl-imx6ul.h97 FSL_IMX6UL_MMDC_ADDR = 0x80000000,
100 FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000,
103 FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000,
106 FSL_IMX6UL_EIM_CS_ADDR = 0x50000000,
109 FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000,
112 FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000,
116 FSL_IMX6UL_UART6_ADDR = 0x021FC000,
118 FSL_IMX6UL_I2C4_ADDR = 0x021F8000,
120 FSL_IMX6UL_UART5_ADDR = 0x021F4000,
121 FSL_IMX6UL_UART4_ADDR = 0x021F0000,
[all …]
H A Dfsl-imx6.h84 #define FSL_IMX6_MMDC_ADDR 0x10000000
85 #define FSL_IMX6_MMDC_SIZE 0xF0000000
86 #define FSL_IMX6_EIM_MEM_ADDR 0x08000000
87 #define FSL_IMX6_EIM_MEM_SIZE 0x8000000
88 #define FSL_IMX6_IPU_2_ADDR 0x02800000
89 #define FSL_IMX6_IPU_2_SIZE 0x400000
90 #define FSL_IMX6_IPU_1_ADDR 0x02400000
91 #define FSL_IMX6_IPU_1_SIZE 0x400000
92 #define FSL_IMX6_MIPI_HSI_ADDR 0x02208000
93 #define FSL_IMX6_MIPI_HSI_SIZE 0x4000
[all …]
/openbmc/u-boot/board/terasic/de10-nano/qts/
H A Diocsr_config.h15 0x00000000,
16 0x00000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x00020080,
22 0x18060000,
23 0x08000000,
24 0x00018020,
[all …]
/openbmc/u-boot/board/terasic/de0-nano-soc/qts/
H A Diocsr_config.h15 0x00000000,
16 0x00000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x00020080,
22 0x18060000,
23 0x08000000,
24 0x00018020,
[all …]
/openbmc/openpower-pnor-code-mgmt/test/
H A Dtest_item_updater_static.cpp22 "TOC@0x00000000 Partitions:\n" in TEST()
24 "ID=00 part 0x00000000..0x00002000 (actual=0x00002000) " in TEST()
26 "ID=01 HBEL 0x00008000..0x0002c000 (actual=0x00024000) " in TEST()
28 "ID=02 GUARD 0x0002c000..0x00031000 (actual=0x00005000) " in TEST()
30 "ID=03 NVRAM 0x00031000..0x000c1000 (actual=0x00090000) " in TEST()
32 "ID=04 SECBOOT 0x000c1000..0x000e5000 (actual=0x00024000) " in TEST()
34 "ID=05 DJVPD 0x000e5000..0x0012d000 (actual=0x00048000) " in TEST()
36 "ID=06 MVPD 0x0012d000..0x001bd000 (actual=0x00090000) " in TEST()
38 "ID=07 CVPD 0x001bd000..0x00205000 (actual=0x00048000) " in TEST()
40 "ID=08 HBB 0x00205000..0x00305000 (actual=0x00100000) " in TEST()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx6sll.dtsi44 #size-cells = <0>;
46 cpu0: cpu@0 {
49 reg = <0>;
85 reg = <0x00a01000 0x1000>,
86 <0x00a00100 0x100>;
92 #size-cells = <0>;
94 ckil: clock@0 {
96 reg = <0>;
97 #clock-cells = <0>;
105 #clock-cells = <0>;
[all …]
H A Dimx6ul.dtsi55 #size-cells = <0>;
57 cpu0: cpu@0 {
60 reg = <0>;
98 reg = <0x00a01000 0x1000>,
99 <0x00a02000 0x1000>,
100 <0x00a04000 0x2000>,
101 <0x00a06000 0x2000>;
106 #clock-cells = <0>;
113 #clock-cells = <0>;
120 #clock-cells = <0>;
[all …]
H A Dimx6sl.dtsi24 memory { device_type = "memory"; reg = <0 0>; };
48 #size-cells = <0>;
50 cpu@0 {
53 reg = <0x0>;
83 reg = <0x00a01000 0x1000>,
84 <0x00a00100 0x100>;
90 #size-cells = <0>;
94 #clock-cells = <0>;
100 #clock-cells = <0>;
114 reg = <0x00900000 0x20000>;
[all …]
H A Dimx6qdl.dtsi56 #clock-cells = <0>;
62 #clock-cells = <0>;
63 clock-frequency = <0>;
68 #clock-cells = <0>;
76 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
84 #size-cells = <0>;
89 lvds-channel@0 {
91 #size-cells = <0>;
92 reg = <0>;
95 port@0 {
[all …]
H A Dimx6sx.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0>;
94 reg = <0x00a01000 0x1000>,
95 <0x00a00100 0x100>;
101 #size-cells = <0>;
103 ckil: clock@0 {
105 reg = <0>;
106 #clock-cells = <0>;
114 #clock-cells = <0>;
[all …]
H A Dimx6ull.dtsi53 #size-cells = <0>;
55 cpu0: cpu@0 {
58 reg = <0>;
90 reg = <0x00a01000 0x1000>,
91 <0x00a02000 0x100>;
96 #size-cells = <0>;
98 ckil: clock@0 {
100 reg = <0>;
101 #clock-cells = <0>;
109 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6sll.dtsi47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
96 #clock-cells = <0>;
97 clock-frequency = <0>;
103 #clock-cells = <0>;
104 clock-frequency = <0>;
117 reg = <0x00900000 0x20000>;
[all …]
H A Dimx6sl.dtsi51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x0>;
86 #clock-cells = <0>;
92 #clock-cells = <0>;
100 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
105 #phy-cells = <0>;
117 reg = <0x00900000 0x20000>;
118 ranges = <0 0x00900000 0x20000>;
128 reg = <0x00a01000 0x1000>,
[all …]
H A Dimx6ul.dtsi58 #size-cells = <0>;
60 cpu0: cpu@0 {
63 reg = <0>;
108 #clock-cells = <0>;
115 #clock-cells = <0>;
122 #clock-cells = <0>;
123 clock-frequency = <0>;
129 #clock-cells = <0>;
130 clock-frequency = <0>;
149 reg = <0x00900000 0x20000>;
[all …]
H A Dimx6qdl.dtsi59 #clock-cells = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #clock-cells = <0>;
78 #size-cells = <0>;
83 lvds-channel@0 {
85 #size-cells = <0>;
86 reg = <0>;
89 port@0 {
90 reg = <0>;
[all …]
H A Dimx6sx.dtsi61 #size-cells = <0>;
63 cpu0: cpu@0 {
66 reg = <0>;
100 #clock-cells = <0>;
107 #clock-cells = <0>;
114 #clock-cells = <0>;
115 clock-frequency = <0>;
121 #clock-cells = <0>;
122 clock-frequency = <0>;
128 #clock-cells = <0>;
[all …]
/openbmc/linux/drivers/soc/tegra/cbb/
H A Dtegra194-cbb.c27 #define ERRLOGGER_0_ID_COREID_0 0x00000000
28 #define ERRLOGGER_0_ID_REVISIONID_0 0x00000004
29 #define ERRLOGGER_0_FAULTEN_0 0x00000008
30 #define ERRLOGGER_0_ERRVLD_0 0x0000000c
31 #define ERRLOGGER_0_ERRCLR_0 0x00000010
32 #define ERRLOGGER_0_ERRLOG0_0 0x00000014
33 #define ERRLOGGER_0_ERRLOG1_0 0x00000018
34 #define ERRLOGGER_0_RSVD_00_0 0x0000001c
35 #define ERRLOGGER_0_ERRLOG3_0 0x00000020
36 #define ERRLOGGER_0_ERRLOG4_0 0x00000024
[all …]