Lines Matching +full:0 +full:x02008000
55 #size-cells = <0>;
57 cpu0: cpu@0 {
60 reg = <0>;
98 reg = <0x00a01000 0x1000>,
99 <0x00a02000 0x1000>,
100 <0x00a04000 0x2000>,
101 <0x00a06000 0x2000>;
106 #clock-cells = <0>;
113 #clock-cells = <0>;
120 #clock-cells = <0>;
121 clock-frequency = <0>;
127 #clock-cells = <0>;
128 clock-frequency = <0>;
147 reg = <0x00900000 0x20000>;
152 reg = <0x01804000 0x2000>;
153 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
154 <0 13 IRQ_TYPE_LEVEL_HIGH>,
155 <0 13 IRQ_TYPE_LEVEL_HIGH>,
156 <0 13 IRQ_TYPE_LEVEL_HIGH>;
167 reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
169 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
178 dmas = <&dma_apbh 0>;
187 reg = <0x02000000 0x100000>;
194 reg = <0x02000000 0x40000>;
200 #size-cells = <0>;
202 reg = <0x02008000 0x4000>;
212 #size-cells = <0>;
214 reg = <0x0200c000 0x4000>;
224 #size-cells = <0>;
226 reg = <0x02010000 0x4000>;
236 #size-cells = <0>;
238 reg = <0x02014000 0x4000>;
249 reg = <0x02018000 0x4000>;
260 reg = <0x02020000 0x4000>;
271 reg = <0x02024000 0x4000>;
280 #sound-dai-cells = <0>;
282 reg = <0x02028000 0x4000>;
288 dmas = <&sdma 35 24 0>,
289 <&sdma 36 24 0>;
295 #sound-dai-cells = <0>;
297 reg = <0x0202c000 0x4000>;
303 dmas = <&sdma 37 24 0>,
304 <&sdma 38 24 0>;
310 #sound-dai-cells = <0>;
312 reg = <0x02030000 0x4000>;
318 dmas = <&sdma 39 24 0>,
319 <&sdma 40 24 0>;
327 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
338 reg = <0x02080000 0x4000>;
349 reg = <0x02084000 0x4000>;
360 reg = <0x02088000 0x4000>;
371 reg = <0x0208c000 0x4000>;
382 reg = <0x02090000 0x4000>;
392 reg = <0x02094000 0x4000>;
402 reg = <0x02098000 0x4000>;
411 reg = <0x0209c000 0x4000>;
418 gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
424 reg = <0x020a0000 0x4000>;
431 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
436 reg = <0x020a4000 0x4000>;
443 gpio-ranges = <&iomuxc 0 65 29>;
448 reg = <0x020a8000 0x4000>;
455 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
460 reg = <0x020ac000 0x4000>;
467 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
472 reg = <0x020b4000 0x4000>;
489 reg = <0x020b8000 0x4000>;
497 reg = <0x020bc000 0x4000>;
504 reg = <0x020c0000 0x4000>;
512 reg = <0x020c4000 0x4000>;
523 reg = <0x020c8000 0x1000>;
533 anatop-reg-offset = <0x120>;
536 anatop-min-bit-val = <0>;
539 anatop-enable-bit = <0>;
548 anatop-reg-offset = <0x140>;
549 anatop-vol-bit-shift = <0>;
551 anatop-delay-reg-offset = <0x170>;
565 anatop-reg-offset = <0x140>;
568 anatop-delay-reg-offset = <0x170>;
579 reg = <0x020c9000 0x1000>;
588 reg = <0x020ca000 0x1000>;
596 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
597 reg = <0x020cc000 0x4000>;
600 compatible = "fsl,sec-v4.0-mon-rtc-lp";
602 offset = <0x34>;
610 offset = <0x38>;
611 mask = <0x60>;
616 compatible = "fsl,sec-v4.0-pwrkey";
625 reg = <0x020d0000 0x4000>;
630 reg = <0x020d4000 0x4000>;
636 reg = <0x020d8000 0x4000>;
644 reg = <0x020dc000 0x4000>;
653 reg = <0x020e0000 0x4000>;
659 reg = <0x020e4000 0x4000>;
664 reg = <0x020e8000 0x4000>;
674 reg = <0x020ec000 0x4000>;
685 reg = <0x020f0000 0x4000>;
696 reg = <0x020f4000 0x4000>;
707 reg = <0x020f8000 0x4000>;
718 reg = <0x020fc000 0x4000>;
732 reg = <0x02100000 0x100000>;
737 reg = <0x02184000 0x200>;
741 fsl,usbmisc = <&usbmisc 0>;
743 ahb-burst-config = <0x0>;
744 tx-burst-size-dword = <0x10>;
745 rx-burst-size-dword = <0x10>;
751 reg = <0x02184200 0x200>;
756 ahb-burst-config = <0x0>;
757 tx-burst-size-dword = <0x10>;
758 rx-burst-size-dword = <0x10>;
765 reg = <0x02184800 0x200>;
770 reg = <0x02188000 0x4000>;
787 reg = <0x02190000 0x4000>;
799 reg = <0x02194000 0x4000>;
811 reg = <0x02198000 0x4000>;
823 #size-cells = <0>;
825 reg = <0x021a0000 0x4000>;
833 #size-cells = <0>;
835 reg = <0x021a4000 0x4000>;
843 #size-cells = <0>;
845 reg = <0x021a8000 0x4000>;
853 reg = <0x021b0000 0x4000>;
858 reg = <0x021c8000 0x4000>;
869 #size-cells = <0>;
871 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
882 reg = <0x021e4000 0x4000>;
891 reg = <0x021e8000 0x4000>;
902 reg = <0x021ec000 0x4000>;
913 reg = <0x021f0000 0x4000>;
924 reg = <0x021f4000 0x4000>;
934 #size-cells = <0>;
936 reg = <0x021f8000 0x4000>;
945 reg = <0x021fc000 0x4000>;