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/openbmc/linux/arch/mips/include/asm/sn/sn0/
H A Daddrs.h57 #define NASID_BITMASK (0x1ffLL)
62 #define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10)
63 #define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3)
70 #define NASID_BITMASK (0xffLL)
76 #define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10)
77 #define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3)
90 ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
106 #define BWIN_WIDGET_MASK 0x7
150 #define MISC_PROM_BASE PHYS_TO_K0(0x01300000)
151 #define MISC_PROM_SIZE 0x200000
[all …]
/openbmc/linux/arch/arm/mach-davinci/
H A Dhardware.h23 #define IO_PHYS UL(0x01c00000)
24 #define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */
25 #define IO_SIZE 0x00400000
H A Ddevices-da8xx.c28 #define DA8XX_TPCC_BASE 0x01c00000
29 #define DA8XX_TPTC0_BASE 0x01c08000
30 #define DA8XX_TPTC1_BASE 0x01c08400
31 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
32 #define DA8XX_I2C0_BASE 0x01c22000
33 #define DA8XX_RTC_BASE 0x01c23000
34 #define DA8XX_PRUSS_MEM_BASE 0x01c30000
35 #define DA8XX_MMCSD0_BASE 0x01c40000
36 #define DA8XX_SPI0_BASE 0x01c41000
37 #define DA830_SPI1_BASE 0x01e12000
[all …]
/openbmc/linux/arch/mips/alchemy/
H A Dboard-gpr.c42 alchemy_gpio_direction_output(4, 0); in gpr_reset()
43 alchemy_gpio_direction_output(5, 0); in gpr_reset()
48 alchemy_gpio_direction_output(1, 0); in gpr_reset()
81 [0] = {
91 .id = 0,
99 * 0x00000000-0x00200000 : "kernel"
100 * 0x00200000-0x00a00000 : "rootfs"
101 * 0x01d00000-0x01f00000 : "config"
102 * 0x01c00000-0x01d00000 : "yamon"
103 * 0x01d00000-0x01d40000 : "yamon env vars"
[all …]
H A Dboard-mtx1.c41 __asm__ __volatile__("jr\t%0" : : "r"(0xbfc00000)); in mtx1_reset()
57 alchemy_gpio_direction_output(204, 0); in board_setup()
64 alchemy_wrsys(~0, AU1000_SYS_TRIOUTCLR); in board_setup()
65 alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */ in board_setup()
68 alchemy_gpio_direction_output(5, 0); /* Disable eth PHY TX_ER */ in board_setup()
72 alchemy_gpio_direction_output(212, 0); /* red off */ in board_setup()
105 .dev_id = "mtx1-wdt.0",
115 .id = 0,
144 .size = 0x01C00000,
145 .offset = 0,
[all …]
/openbmc/u-boot/configs/
H A Dam57xx_hs_evm_defconfig5 CONFIG_SYS_MALLOC_F_LEN=0x2000
7 CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
8 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
9 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
50 CONFIG_FASTBOOT_BUF_ADDR=0x82000000
51 CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
63 CONFIG_SF_DEFAULT_MODE=0
93 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
94 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
H A Dam57xx_hs_evm_usb_defconfig5 CONFIG_SYS_MALLOC_F_LEN=0x2000
7 CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
8 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
9 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
10 CONFIG_ISW_ENTRY_ADDR=0x40306d50
55 CONFIG_FASTBOOT_BUF_ADDR=0x82000000
56 CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
68 CONFIG_SF_DEFAULT_MODE=0
99 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
100 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
H A Ddra7xx_hs_evm_defconfig5 CONFIG_SYS_MALLOC_F_LEN=0x18000
7 CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
8 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
9 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
41 CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x9000
58 CONFIG_FASTBOOT_BUF_ADDR=0x82000000
59 CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
75 CONFIG_SF_DEFAULT_MODE=0
109 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
110 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
H A Dam43xx_hs_evm_defconfig5 CONFIG_SYS_MALLOC_F_LEN=0x2000
7 CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
8 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
9 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
10 CONFIG_ISW_ENTRY_ADDR=0x403018e0
34 CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
35 CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup…
70 CONFIG_USB_GADGET_VENDOR_NUM=0x0403
71 CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
H A Ddra7xx_hs_evm_usb_defconfig5 CONFIG_SYS_MALLOC_F_LEN=0x18000
7 CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
8 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
9 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
10 CONFIG_ISW_ENTRY_ADDR=0x40306d50
46 CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x9000
62 CONFIG_FASTBOOT_BUF_ADDR=0x82000000
63 CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
79 CONFIG_SF_DEFAULT_MODE=0
114 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
[all …]
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dallwinner,sun50i-h6-vpu-g2.yaml61 reg = <0x01c00000 0x1000>;
/openbmc/linux/arch/mips/include/asm/mach-rc32434/
H A Ddma.h17 #define DMA0_BASE_ADDR 0x18040000
31 #define DMA_DESC_COUNT_BIT 0
32 #define DMA_DESC_COUNT_MSK 0x0003ffff
34 #define DMA_DESC_DS_MSK 0x00300000
37 #define DMA_DESC_DEV_CMD_MSK 0x01c00000
40 #define DMA_DESC_DEV_CMD_BYTE 0
71 #define DMA_CHAN_RUN_BIT (1 << 0)
74 #define DMA_CHAN_MODE_MSK 0x0000000c
75 #define DMA_CHAN_MODE_AUTO 0
82 #define DMA_STAT_FINI (1 << 0)
[all …]
/openbmc/linux/drivers/gpu/drm/mcde/
H A Dmcde_drm.h13 #define MCDE_CR 0x00000000
14 #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_SHIFT 0
15 #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_MASK 0x0000003F
22 #define MCDE_CONF0 0x00000004
23 #define MCDE_CONF0_SYNCMUX0 BIT(0)
32 #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x00007000
34 #define MCDE_CONF0_OUTMUX0_MASK 0x00070000
36 #define MCDE_CONF0_OUTMUX1_MASK 0x00380000
38 #define MCDE_CONF0_OUTMUX2_MASK 0x01C00000
40 #define MCDE_CONF0_OUTMUX3_MASK 0x0E000000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dsyscon.yaml119 reg = <0x01c00000 0x1000>;
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun9i.h12 #define REGS_AHB0_BASE 0x01C00000
13 #define REGS_AHB1_BASE 0x00800000
14 #define REGS_AHB2_BASE 0x03000000
15 #define REGS_APB0_BASE 0x06000000
16 #define REGS_APB1_BASE 0x07000000
17 #define REGS_RCPUS_BASE 0x08000000
19 #define SUNXI_SRAM_D_BASE 0x08100000
22 #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
23 #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
25 #define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
[all …]
H A Dcpu_sun4i.h11 #define SUNXI_SRAM_A1_BASE 0x00000000
14 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
15 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
16 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
17 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
18 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
20 #define SUNXI_DE2_BASE 0x01000000
23 #define SUNXI_CPUCFG_BASE 0x01700000
26 #define SUNXI_SRAMC_BASE 0x01c00000
27 #define SUNXI_DRAMC_BASE 0x01c01000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sram/
H A Dallwinner,sun4i-a10-system-control.yaml115 reg = <0x01c00000 0x30>;
120 sram_a: sram@0 {
122 reg = <0x00000000 0xc000>;
125 ranges = <0 0x00000000 0xc000>;
129 reg = <0x8000 0x4000>;
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie-ep.yaml187 reg = <0x01c00000 0x3000>,
188 <0x40000000 0xf1d>,
189 <0x40000f20 0xc8>,
190 <0x40001000 0x1000>,
191 <0x40002000 0x1000>,
192 <0x01c03000 0x3000>;
206 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8569mds.dts30 reg = <0x0 0xe0005000 0x0 0x1000>;
32 ranges = <0x0 0x0 0x0 0xfe000000 0x02000000
33 0x1 0x0 0x0 0xf8000000 0x00008000
34 0x2 0x0 0x0 0xf0000000 0x04000000
35 0x3 0x0 0x0 0xfc000000 0x00008000
36 0x4 0x0 0x0 0xf8008000 0x00008000
37 0x5 0x0 0x0 0xf8010000 0x00008000>;
39 nor@0,0 {
43 reg = <0x0 0x0 0x02000000>;
46 partition@0 {
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsun8i-h3.dtsi71 #size-cells = <0>;
73 cpu0: cpu@0 {
76 reg = <0>;
125 reg = <0x01c00000 0x30>;
132 reg = <0x01d00000 0x80000>;
135 ranges = <0 0x01d00000 0x80000>;
137 ve_sram: sram-section@0 {
140 reg = <0x000000 0x80000>;
147 reg = <0x01c40000 0x10000>;
/openbmc/linux/arch/mips/include/asm/mach-loongson64/
H A Dloongson.h62 for (x = 0; x < 100000; x++) \
75 #define LOONGSON_FLASH_BASE 0x1c000000
76 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
79 #define LOONGSON_LIO0_BASE 0x1e000000
80 #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
83 #define LOONGSON_BOOT_BASE 0x1fc00000
84 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
86 #define LOONGSON_REG_BASE 0x1fe00000
87 #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
90 #define LOONGSON3_REG_BASE 0x3ff00000
[all …]
/openbmc/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h5.dtsi11 #size-cells = <0>;
13 cpu0: cpu@0 {
16 reg = <0>;
84 reg = <0x01c00000 0x1000>;
91 reg = <0x00018000 0x1c000>;
94 ranges = <0 0x00018000 0x1c000>;
96 ve_sram: sram-section@0 {
99 reg = <0x000000 0x1c000>;
106 reg = <0x01c0e000 0x1000>;
117 reg = <0x01c15000 0x1000>;
[all …]
/openbmc/linux/arch/mips/include/asm/mach-loongson2ef/
H A Dloongson.h51 for (x = 0; x < 100000; x++) \
60 #define LOONGSON_FLASH_BASE 0x1c000000
61 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
64 #define LOONGSON_LIO0_BASE 0x1e000000
65 #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
68 #define LOONGSON_BOOT_BASE 0x1fc00000
69 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
71 #define LOONGSON_REG_BASE 0x1fe00000
72 #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
75 #define LOONGSON_LIO1_BASE 0x1ff00000
[all …]
/openbmc/u-boot/include/
H A Dfsl_qe.h20 #define QE_DATAONLY_BASE 0
37 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
38 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
39 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
40 #define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
50 #define QE_CR_FLG 0x00010000
51 #define QE_RESET 0x80000000
52 #define QE_INIT_TX_RX 0x00000000
53 #define QE_INIT_RX 0x00000001
54 #define QE_INIT_TX 0x00000002
[all …]
/openbmc/qemu/hw/arm/
H A Dallwinner-a10.c32 #define AW_A10_SRAM_A_BASE 0x00000000
33 #define AW_A10_DRAMC_BASE 0x01c01000
34 #define AW_A10_MMC0_BASE 0x01c0f000
35 #define AW_A10_CCM_BASE 0x01c20000
36 #define AW_A10_PIC_REG_BASE 0x01c20400
37 #define AW_A10_PIT_REG_BASE 0x01c20c00
38 #define AW_A10_UART0_REG_BASE 0x01c28000
39 #define AW_A10_SPI0_BASE 0x01c05000
40 #define AW_A10_EMAC_BASE 0x01c0b000
41 #define AW_A10_EHCI_BASE 0x01c14000
[all …]

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