Lines Matching +full:0 +full:x01c00000
20 #define QE_DATAONLY_BASE 0
37 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
38 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
39 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
40 #define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
50 #define QE_CR_FLG 0x00010000
51 #define QE_RESET 0x80000000
52 #define QE_INIT_TX_RX 0x00000000
53 #define QE_INIT_RX 0x00000001
54 #define QE_INIT_TX 0x00000002
55 #define QE_ENTER_HUNT_MODE 0x00000003
56 #define QE_STOP_TX 0x00000004
57 #define QE_GRACEFUL_STOP_TX 0x00000005
58 #define QE_RESTART_TX 0x00000006
59 #define QE_SWITCH_COMMAND 0x00000007
60 #define QE_SET_GROUP_ADDRESS 0x00000008
61 #define QE_INSERT_CELL 0x00000009
62 #define QE_ATM_TRANSMIT 0x0000000a
63 #define QE_CELL_POOL_GET 0x0000000b
64 #define QE_CELL_POOL_PUT 0x0000000c
65 #define QE_IMA_HOST_CMD 0x0000000d
66 #define QE_ATM_MULTI_THREAD_INIT 0x00000011
67 #define QE_ASSIGN_PAGE 0x00000012
68 #define QE_START_FLOW_CONTROL 0x00000014
69 #define QE_STOP_FLOW_CONTROL 0x00000015
70 #define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
71 #define QE_GRACEFUL_STOP_RX 0x0000001a
72 #define QE_RESTART_RX 0x0000001b
76 #define QE_CR_SUBBLOCK_INVALID 0x00000000
77 #define QE_CR_SUBBLOCK_USB 0x03200000
78 #define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
79 #define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
80 #define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
81 #define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
82 #define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
83 #define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
84 #define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
85 #define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
86 #define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
87 #define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
88 #define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
89 #define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
90 #define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
91 #define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
92 #define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
93 #define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
94 #define QE_CR_SUBBLOCK_MCC1 0x03800000
95 #define QE_CR_SUBBLOCK_MCC2 0x03a00000
96 #define QE_CR_SUBBLOCK_MCC3 0x03000000
97 #define QE_CR_SUBBLOCK_IDMA1 0x02800000
98 #define QE_CR_SUBBLOCK_IDMA2 0x02a00000
99 #define QE_CR_SUBBLOCK_IDMA3 0x02c00000
100 #define QE_CR_SUBBLOCK_IDMA4 0x02e00000
101 #define QE_CR_SUBBLOCK_HPAC 0x01e00000
102 #define QE_CR_SUBBLOCK_SPI1 0x01400000
103 #define QE_CR_SUBBLOCK_SPI2 0x01600000
104 #define QE_CR_SUBBLOCK_RAND 0x01c00000
105 #define QE_CR_SUBBLOCK_TIMER 0x01e00000
106 #define QE_CR_SUBBLOCK_GENERAL 0x03c00000
110 #define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
111 #define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
112 #define QE_CR_PROTOCOL_ATM_POS 0x0A
113 #define QE_CR_PROTOCOL_ETHERNET 0x0C
114 #define QE_CR_PROTOCOL_L2_SWITCH 0x0D
124 COMM_DIR_NONE = 0,
133 QE_CLK_NONE = 0,
179 #define QE_CMXGCR_MII_ENET_MNG_MASK 0x00007000
184 #define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
188 #define QE_BRGC_ENABLE 0x00010000
190 #define QE_BRGC_DIVISOR_MAX 0xFFF
195 #define QE_SDSR_BER1 0x02000000
196 #define QE_SDSR_BER2 0x01000000
198 #define QE_SDMR_GLB_1_MSK 0x80000000
199 #define QE_SDMR_ADR_SEL 0x20000000
200 #define QE_SDMR_BER1_MSK 0x02000000
201 #define QE_SDMR_BER2_MSK 0x01000000
202 #define QE_SDMR_EB1_MSK 0x00800000
203 #define QE_SDMR_ER1_MSK 0x00080000
204 #define QE_SDMR_ER2_MSK 0x00040000
205 #define QE_SDMR_CEN_MASK 0x0000E000
206 #define QE_SDMR_SBER_1 0x00000200
207 #define QE_SDMR_SBER_2 0x00000200
208 #define QE_SDMR_EB1_PR_MASK 0x000000C0
209 #define QE_SDMR_ER1_PR 0x00000008
216 #define QE_SDEBCR_BA_MASK 0x01FFFFFF
219 #define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
220 #define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
221 #define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
224 #define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
225 #define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
226 #define QE_IRAM_READY 0x80000000
239 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
252 u32 traps[16]; /* Trap addresses, 0 == ignore */