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/openbmc/linux/drivers/usb/storage/
H A Dunusual_alauda.h9 UNUSUAL_DEV( 0x0584, 0x0008, 0x0102, 0x0102,
12 USB_SC_SCSI, USB_PR_ALAUDA, init_alauda, 0),
14 UNUSUAL_DEV( 0x07b4, 0x010a, 0x0102, 0x0102,
17 USB_SC_SCSI, USB_PR_ALAUDA, init_alauda, 0),
/openbmc/linux/sound/soc/codecs/
H A Drt712-sdca-dmic.h34 #define CH_01 0x01
35 #define CH_02 0x02
36 #define CH_03 0x03
37 #define CH_04 0x04
40 { 0x201a, 0x00 },
41 { 0x201b, 0x00 },
42 { 0x201c, 0x00 },
43 { 0x201d, 0x00 },
44 { 0x201e, 0x00 },
45 { 0x201f, 0x00 },
[all …]
H A Drt722-sdca-sdw.h15 { 0x202d, 0x00 },
16 { 0x2f01, 0x00 },
17 { 0x2f02, 0x09 },
18 { 0x2f03, 0x00 },
19 { 0x2f04, 0x00 },
20 { 0x2f05, 0x0b },
21 { 0x2f06, 0x01 },
22 { 0x2f08, 0x00 },
23 { 0x2f09, 0x00 },
24 { 0x2f0a, 0x00 },
[all …]
H A Drt1019.h11 #define RT1019_DEVICE_ID_VAL 0x1019
12 #define RT1019_DEVICE_ID_VAL2 0x6731
14 #define RT1019_RESET 0x0000
15 #define RT1019_IDS_CTRL 0x0011
16 #define RT1019_ASEL_CTRL 0x0013
17 #define RT1019_PWR_STRP_2 0x0019
18 #define RT1019_BEEP_TONE 0x001b
19 #define RT1019_VER_ID 0x005c
20 #define RT1019_VEND_ID_1 0x005e
21 #define RT1019_VEND_ID_2 0x005f
[all …]
H A Dmax98373-sdw.h10 #define MAX98373_R0040_SCP_INIT_STAT_1 0x0040
11 #define MAX98373_R0041_SCP_INIT_MASK_1 0x0041
12 #define MAX98373_R0042_SCP_INIT_STAT_2 0x0042
13 #define MAX98373_R0044_SCP_CTRL 0x0044
14 #define MAX98373_R0045_SCP_SYSTEM_CTRL 0x0045
15 #define MAX98373_R0046_SCP_DEV_NUMBER 0x0046
16 #define MAX98373_R0050_SCP_DEV_ID_0 0x0050
17 #define MAX98373_R0051_SCP_DEV_ID_1 0x0051
18 #define MAX98373_R0052_SCP_DEV_ID_2 0x0052
19 #define MAX98373_R0053_SCP_DEV_ID_3 0x0053
[all …]
H A Drt1015.h17 #define RT1015_DEVICE_ID_VAL 0x1011
18 #define RT1015_DEVICE_ID_VAL2 0x1015
20 #define RT1015_RESET 0x0000
21 #define RT1015_CLK2 0x0004
22 #define RT1015_CLK3 0x0006
23 #define RT1015_PLL1 0x000a
24 #define RT1015_PLL2 0x000c
25 #define RT1015_DUM_RW1 0x000e
26 #define RT1015_DUM_RW2 0x0010
27 #define RT1015_DUM_RW3 0x0012
[all …]
/openbmc/linux/arch/sh/include/mach-common/mach/
H A Dhighlander.h6 #define PA_NORFLASH_ADDR 0x00000000
7 #define PA_NORFLASH_SIZE 0x04000000
10 #define PA_BCR 0xa4000000 /* FPGA */
13 #define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
14 #define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
15 #define PA_IRLPRI1 (PA_BCR+0x0004) /* Interrupt Priorty 1 */
16 #define PA_IRLPRI2 (PA_BCR+0x0006) /* Interrupt Priorty 2 */
17 #define PA_IRLPRI3 (PA_BCR+0x0008) /* Interrupt Priorty 3 */
18 #define PA_IRLPRI4 (PA_BCR+0x000a) /* Interrupt Priorty 4 */
19 #define PA_RSTCTL (PA_BCR+0x000c) /* Reset Control */
[all …]
/openbmc/linux/scripts/mod/
H A Dmk_elfconfig.c17 if (memcmp(ei, ELFMAG, SELFMAG) != 0) { in main()
48 endian_test.s = 0x0102; in main()
49 if (memcmp(endian_test.c, "\x01\x02", 2) == 0) in main()
51 else if (memcmp(endian_test.c, "\x02\x01", 2) == 0) in main()
56 return 0; in main()
/openbmc/linux/include/uapi/linux/
H A Dv4l2-common.h27 #define V4L2_SEL_TGT_CROP 0x0000
29 #define V4L2_SEL_TGT_CROP_DEFAULT 0x0001
31 #define V4L2_SEL_TGT_CROP_BOUNDS 0x0002
33 #define V4L2_SEL_TGT_NATIVE_SIZE 0x0003
35 #define V4L2_SEL_TGT_COMPOSE 0x0100
37 #define V4L2_SEL_TGT_COMPOSE_DEFAULT 0x0101
39 #define V4L2_SEL_TGT_COMPOSE_BOUNDS 0x0102
41 #define V4L2_SEL_TGT_COMPOSE_PADDED 0x0103
44 #define V4L2_SEL_FLAG_GE (1 << 0)
/openbmc/linux/Documentation/userspace-api/media/v4l/
H A Dv4l2-selection-targets.rst25 :stub-columns: 0
33 - 0x0000
38 - 0x0001
45 - 0x0002
51 - 0x0003
57 - 0x0100
62 - 0x0101
67 - 0x0102
73 - 0x0103
/openbmc/u-boot/include/
H A Dcp1250.h4 * Constant CP1250 contains the Unicode code points for characters 0x80 - 0xff
8 0x20ac, 0x0000, 0x201a, 0x0000, \
9 0x201e, 0x2026, 0x2020, 0x2021, \
10 0x0000, 0x2030, 0x0160, 0x2039, \
11 0x015a, 0x0164, 0x017d, 0x0179, \
12 0x0000, 0x2018, 0x2019, 0x201c, \
13 0x201d, 0x2022, 0x2013, 0x2014, \
14 0x0000, 0x2122, 0x0161, 0x203a, \
15 0x015b, 0x0165, 0x017e, 0x017a, \
16 0x00a0, 0x02c7, 0x02d8, 0x0141, \
[all …]
H A Dpci_ids.h12 #define PCI_CLASS_NOT_DEFINED 0x0000
13 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
15 #define PCI_BASE_CLASS_STORAGE 0x01
16 #define PCI_CLASS_STORAGE_SCSI 0x0100
17 #define PCI_CLASS_STORAGE_IDE 0x0101
18 #define PCI_CLASS_STORAGE_FLOPPY 0x0102
19 #define PCI_CLASS_STORAGE_IPI 0x0103
20 #define PCI_CLASS_STORAGE_RAID 0x0104
21 #define PCI_CLASS_STORAGE_SATA 0x0106
22 #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
[all …]
/openbmc/linux/include/pcmcia/
H A Dciscode.h17 #define MANFID_3COM 0x0101
18 #define PRODID_3COM_3CXEM556 0x0035
19 #define PRODID_3COM_3CCFEM556 0x0556
20 #define PRODID_3COM_3C562 0x0562
22 #define MANFID_ACCTON 0x01bf
23 #define PRODID_ACCTON_EN2226 0x010a
25 #define MANFID_ADAPTEC 0x012f
26 #define PRODID_ADAPTEC_SCSI 0x0001
28 #define MANFID_ATT 0xffff
29 #define PRODID_ATT_KIT 0x0100
[all …]
/openbmc/linux/drivers/media/rc/keymaps/
H A Drc-dvico-mce.c12 { 0x0102, KEY_TV },
13 { 0x010e, KEY_MP3 },
14 { 0x011a, KEY_DVD },
15 { 0x011e, KEY_FAVORITES },
16 { 0x0116, KEY_SETUP },
17 { 0x0146, KEY_POWER2 },
18 { 0x010a, KEY_EPG },
19 { 0x0149, KEY_BACK },
20 { 0x014d, KEY_MENU },
21 { 0x0151, KEY_UP },
[all …]
/openbmc/linux/arch/powerpc/boot/
H A Dredboot.h20 unsigned int bi_tag; /* Should be 0x42444944 "BDID" */
23 unsigned int bi_bdate; /* bootstrap date, i.e. 0x19971106 */
53 #define BI_REV 0x0102 /* Version 1.02 */
/openbmc/linux/drivers/media/usb/gspca/
H A Dxirlink_cit.c29 module_param(ibm_netcam_pro, int, 0);
44 #define CIT_MODEL0 0 /* bcd version 0.01 cams ie the xvp-500 */
125 {0, 0x0000, 0x010c},
126 {0, 0x0006, 0x012c},
127 {0, 0x0078, 0x012d},
128 {0, 0x0046, 0x012f},
129 {0, 0xd141, 0x0124},
130 {0, 0x0000, 0x0127},
131 {0, 0xfea8, 0x0124},
132 {1, 0x0000, 0x0116},
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/smuio/
H A Dsmuio_11_0_0_offset.h27 // base address: 0x5a000
28 …SMUSVI0_TEL_PLANE0 0x0004
29 …ne mmSMUSVI0_TEL_PLANE0_BASE_IDX 0
30 …SMUIO_MCM_CONFIG 0x0024
31 …ne mmSMUIO_MCM_CONFIG_BASE_IDX 0
32 …CKSVII2C_IC_CON 0x0040
33 …ne mmCKSVII2C_IC_CON_BASE_IDX 0
34 …CKSVII2C_IC_TAR 0x0041
35 …ne mmCKSVII2C_IC_TAR_BASE_IDX 0
36 …CKSVII2C_IC_SAR 0x0042
[all …]
/openbmc/linux/arch/s390/include/asm/
H A Dipl.h49 #define IPL_MAX_SUPPORTED_VERSION (0)
147 DIAG308_CLEAR_RESET = 0,
162 DIAG308_RC_OK = 0x0001,
163 DIAG308_RC_NOCONFIG = 0x0102,
/openbmc/linux/include/linux/
H A Dpldmfw.h10 #define PLDM_DEVICE_UPDATE_CONTINUE_AFTER_FAIL BIT(0)
12 #define PLDM_STRING_TYPE_UNKNOWN 0
45 #define PLDM_DESC_ID_PCI_VENDOR_ID 0x0000
46 #define PLDM_DESC_ID_IANA_ENTERPRISE_ID 0x0001
47 #define PLDM_DESC_ID_UUID 0x0002
48 #define PLDM_DESC_ID_PNP_VENDOR_ID 0x0003
49 #define PLDM_DESC_ID_ACPI_VENDOR_ID 0x0004
50 #define PLDM_DESC_ID_PCI_DEVICE_ID 0x0100
51 #define PLDM_DESC_ID_PCI_SUBVENDOR_ID 0x0101
52 #define PLDM_DESC_ID_PCI_SUBDEV_ID 0x0102
[all …]
/openbmc/linux/drivers/net/ethernet/wangxun/ngbe/
H A Dngbe_type.h12 #define NGBE_DEV_ID_EM_WX1860AL_W 0x0100
13 #define NGBE_DEV_ID_EM_WX1860A2 0x0101
14 #define NGBE_DEV_ID_EM_WX1860A2S 0x0102
15 #define NGBE_DEV_ID_EM_WX1860A4 0x0103
16 #define NGBE_DEV_ID_EM_WX1860A4S 0x0104
17 #define NGBE_DEV_ID_EM_WX1860AL2 0x0105
18 #define NGBE_DEV_ID_EM_WX1860AL2S 0x0106
19 #define NGBE_DEV_ID_EM_WX1860AL4 0x0107
20 #define NGBE_DEV_ID_EM_WX1860AL4S 0x0108
21 #define NGBE_DEV_ID_EM_WX1860LC 0x0109
[all …]
/openbmc/qemu/hw/s390x/
H A Dipl.h22 #define DIAG308_FLAGS_LP_VALID 0x80
37 S390_RESET_EXTERNAL = 0,
47 #define QIPL_ADDRESS 0xcc
50 #define QIPL_FLAG_BM_OPTS_CMD 0x80
51 #define QIPL_FLAG_BM_OPTS_ZIPL 0x40
86 #define DIAG_308_RC_OK 0x0001
87 #define DIAG_308_RC_NO_CONF 0x0102
88 #define DIAG_308_RC_INVALID 0x0402
89 #define DIAG_308_RC_NO_PV_CONF 0x0902
90 #define DIAG_308_RC_INVAL_FOR_PV 0x0a02
[all …]
/openbmc/linux/include/scsi/fc/
H A Dfc_ms.h25 #define FC_FDMI_SUBTYPE 0x10 /* fs_ct_hdr.ct_fs_subtype */
37 FC_FDMI_GRHL = 0x0100, /* Get Registered HBA List */
38 FC_FDMI_GHAT = 0x0101, /* Get HBA Attributes */
39 FC_FDMI_GRPL = 0x0102, /* Get Registered Port List */
40 FC_FDMI_GPAT = 0x0110, /* Get Port Attributes */
41 FC_FDMI_RHBA = 0x0200, /* Register HBA */
42 FC_FDMI_RHAT = 0x0201, /* Register HBA Attributes */
43 FC_FDMI_RPRT = 0x0210, /* Register Port */
44 FC_FDMI_RPA = 0x0211, /* Register Port Attributes */
45 FC_FDMI_DHBA = 0x0300, /* Deregister HBA */
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/hdp/
H A Dhdp_4_4_2_offset.h29 // base address: 0x3c80
30 …HDP_MMHUB_TLVL 0x0000
31 …e regHDP_MMHUB_TLVL_BASE_IDX 0
32 …HDP_MMHUB_UNITID 0x0001
33 …e regHDP_MMHUB_UNITID_BASE_IDX 0
34 …HDP_NONSURFACE_BASE 0x0040
35 …e regHDP_NONSURFACE_BASE_BASE_IDX 0
36 …HDP_NONSURFACE_INFO 0x0041
37 …e regHDP_NONSURFACE_INFO_BASE_IDX 0
38 …HDP_NONSURFACE_BASE_HI 0x0042
[all …]
H A Dhdp_5_0_0_offset.h27 // base address: 0x3c80
28 …HDP_MMHUB_TLVL 0x0000
29 …ne mmHDP_MMHUB_TLVL_BASE_IDX 0
30 …HDP_MMHUB_UNITID 0x0001
31 …ne mmHDP_MMHUB_UNITID_BASE_IDX 0
32 …HDP_NONSURFACE_BASE 0x0040
33 …ne mmHDP_NONSURFACE_BASE_BASE_IDX 0
34 …HDP_NONSURFACE_INFO 0x0041
35 …ne mmHDP_NONSURFACE_INFO_BASE_IDX 0
36 …HDP_NONSURFACE_BASE_HI 0x0042
[all …]
H A Dhdp_5_2_1_offset.h29 // base address: 0x3c80
30 …HDP_MMHUB_TLVL 0x0000
31 …e regHDP_MMHUB_TLVL_BASE_IDX 0
32 …HDP_MMHUB_UNITID 0x0001
33 …e regHDP_MMHUB_UNITID_BASE_IDX 0
34 …HDP_NONSURFACE_BASE 0x0040
35 …e regHDP_NONSURFACE_BASE_BASE_IDX 0
36 …HDP_NONSURFACE_INFO 0x0041
37 …e regHDP_NONSURFACE_INFO_BASE_IDX 0
38 …HDP_NONSURFACE_BASE_HI 0x0042
[all …]

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