1df310074SJack Yu // SPDX-License-Identifier: GPL-2.0 2df310074SJack Yu // 3df310074SJack Yu // rt1015.h -- RT1015 ALSA SoC audio amplifier driver 4df310074SJack Yu // 5df310074SJack Yu // Copyright 2019 Realtek Semiconductor Corp. 6df310074SJack Yu // Author: Jack Yu <jack.yu@realtek.com> 7df310074SJack Yu // 8df310074SJack Yu // This program is free software; you can redistribute it and/or modify 9df310074SJack Yu // it under the terms of the GNU General Public License version 2 as 10df310074SJack Yu // published by the Free Software Foundation. 11df310074SJack Yu // 12df310074SJack Yu 13df310074SJack Yu #ifndef __RT1015_H__ 14df310074SJack Yu #define __RT1015_H__ 1593bd813cSJack Yu #include <sound/rt1015.h> 16df310074SJack Yu 17df310074SJack Yu #define RT1015_DEVICE_ID_VAL 0x1011 18df310074SJack Yu #define RT1015_DEVICE_ID_VAL2 0x1015 19df310074SJack Yu 20df310074SJack Yu #define RT1015_RESET 0x0000 21df310074SJack Yu #define RT1015_CLK2 0x0004 22df310074SJack Yu #define RT1015_CLK3 0x0006 23df310074SJack Yu #define RT1015_PLL1 0x000a 24df310074SJack Yu #define RT1015_PLL2 0x000c 25e74a1e7eSJack Yu #define RT1015_DUM_RW1 0x000e 26e74a1e7eSJack Yu #define RT1015_DUM_RW2 0x0010 27e74a1e7eSJack Yu #define RT1015_DUM_RW3 0x0012 28e74a1e7eSJack Yu #define RT1015_DUM_RW4 0x0014 29e74a1e7eSJack Yu #define RT1015_DUM_RW5 0x0016 30e74a1e7eSJack Yu #define RT1015_DUM_RW6 0x0018 31df310074SJack Yu #define RT1015_CLK_DET 0x0020 32df310074SJack Yu #define RT1015_SIL_DET 0x0022 33df310074SJack Yu #define RT1015_CUSTOMER_ID 0x0076 34df310074SJack Yu #define RT1015_PCODE_FWVER 0x0078 35df310074SJack Yu #define RT1015_VER_ID 0x007a 36df310074SJack Yu #define RT1015_VENDOR_ID 0x007c 37df310074SJack Yu #define RT1015_DEVICE_ID 0x007d 38df310074SJack Yu #define RT1015_PAD_DRV1 0x00f0 39df310074SJack Yu #define RT1015_PAD_DRV2 0x00f2 40df310074SJack Yu #define RT1015_GAT_BOOST 0x00f3 41df310074SJack Yu #define RT1015_PRO_ALT 0x00f4 42e74a1e7eSJack Yu #define RT1015_OSCK_STA 0x00f6 43df310074SJack Yu #define RT1015_MAN_I2C 0x0100 44df310074SJack Yu #define RT1015_DAC1 0x0102 45df310074SJack Yu #define RT1015_DAC2 0x0104 46df310074SJack Yu #define RT1015_DAC3 0x0106 47df310074SJack Yu #define RT1015_ADC1 0x010c 48df310074SJack Yu #define RT1015_ADC2 0x010e 49df310074SJack Yu #define RT1015_TDM_MASTER 0x0111 50df310074SJack Yu #define RT1015_TDM_TCON 0x0112 51df310074SJack Yu #define RT1015_TDM1_1 0x0114 52df310074SJack Yu #define RT1015_TDM1_2 0x0116 53df310074SJack Yu #define RT1015_TDM1_3 0x0118 54df310074SJack Yu #define RT1015_TDM1_4 0x011a 55df310074SJack Yu #define RT1015_TDM1_5 0x011c 56df310074SJack Yu #define RT1015_MIXER1 0x0300 57df310074SJack Yu #define RT1015_MIXER2 0x0302 58df310074SJack Yu #define RT1015_ANA_PROTECT1 0x0311 59df310074SJack Yu #define RT1015_ANA_CTRL_SEQ1 0x0313 60df310074SJack Yu #define RT1015_ANA_CTRL_SEQ2 0x0314 61df310074SJack Yu #define RT1015_VBAT_DET_DEB 0x031a 62df310074SJack Yu #define RT1015_VBAT_VOLT_DET1 0x031c 63df310074SJack Yu #define RT1015_VBAT_VOLT_DET2 0x031d 64df310074SJack Yu #define RT1015_VBAT_TEST_OUT1 0x031e 65df310074SJack Yu #define RT1015_VBAT_TEST_OUT2 0x031f 66df310074SJack Yu #define RT1015_VBAT_PROT_ATT 0x0320 67df310074SJack Yu #define RT1015_VBAT_DET_CODE 0x0321 68df310074SJack Yu #define RT1015_PWR1 0x0322 69df310074SJack Yu #define RT1015_PWR4 0x0328 70df310074SJack Yu #define RT1015_PWR5 0x0329 71df310074SJack Yu #define RT1015_PWR6 0x032a 72df310074SJack Yu #define RT1015_PWR7 0x032b 73df310074SJack Yu #define RT1015_PWR8 0x032c 74df310074SJack Yu #define RT1015_PWR9 0x032d 75df310074SJack Yu #define RT1015_CLASSD_SEQ 0x032e 76df310074SJack Yu #define RT1015_SMART_BST_CTRL1 0x0330 77df310074SJack Yu #define RT1015_SMART_BST_CTRL2 0x0332 78df310074SJack Yu #define RT1015_ANA_CTRL1 0x0334 79df310074SJack Yu #define RT1015_ANA_CTRL2 0x0336 80df310074SJack Yu #define RT1015_PWR_STATE_CTRL 0x0338 81e74a1e7eSJack Yu #define RT1015_MONO_DYNA_CTRL 0x04fa 82e74a1e7eSJack Yu #define RT1015_MONO_DYNA_CTRL1 0x04fc 83e74a1e7eSJack Yu #define RT1015_MONO_DYNA_CTRL2 0x04fe 84e74a1e7eSJack Yu #define RT1015_MONO_DYNA_CTRL3 0x0500 85e74a1e7eSJack Yu #define RT1015_MONO_DYNA_CTRL4 0x0502 86e74a1e7eSJack Yu #define RT1015_MONO_DYNA_CTRL5 0x0504 87df310074SJack Yu #define RT1015_SPK_VOL 0x0506 88df310074SJack Yu #define RT1015_SHORT_DETTOP1 0x0508 89df310074SJack Yu #define RT1015_SHORT_DETTOP2 0x050a 90df310074SJack Yu #define RT1015_SPK_DC_DETECT1 0x0519 91df310074SJack Yu #define RT1015_SPK_DC_DETECT2 0x051a 92df310074SJack Yu #define RT1015_SPK_DC_DETECT3 0x051b 93df310074SJack Yu #define RT1015_SPK_DC_DETECT4 0x051d 94df310074SJack Yu #define RT1015_SPK_DC_DETECT5 0x051f 95df310074SJack Yu #define RT1015_BAT_RPO_STEP1 0x0536 96df310074SJack Yu #define RT1015_BAT_RPO_STEP2 0x0538 97df310074SJack Yu #define RT1015_BAT_RPO_STEP3 0x053a 98df310074SJack Yu #define RT1015_BAT_RPO_STEP4 0x053c 99df310074SJack Yu #define RT1015_BAT_RPO_STEP5 0x053d 100df310074SJack Yu #define RT1015_BAT_RPO_STEP6 0x053e 101df310074SJack Yu #define RT1015_BAT_RPO_STEP7 0x053f 102df310074SJack Yu #define RT1015_BAT_RPO_STEP8 0x0540 103df310074SJack Yu #define RT1015_BAT_RPO_STEP9 0x0541 104df310074SJack Yu #define RT1015_BAT_RPO_STEP10 0x0542 105df310074SJack Yu #define RT1015_BAT_RPO_STEP11 0x0543 106df310074SJack Yu #define RT1015_BAT_RPO_STEP12 0x0544 107df310074SJack Yu #define RT1015_SPREAD_SPEC1 0x0568 108df310074SJack Yu #define RT1015_SPREAD_SPEC2 0x056a 109df310074SJack Yu #define RT1015_PAD_STATUS 0x1000 110df310074SJack Yu #define RT1015_PADS_PULLING_CTRL1 0x1002 111df310074SJack Yu #define RT1015_PADS_DRIVING 0x1006 112df310074SJack Yu #define RT1015_SYS_RST1 0x1007 113df310074SJack Yu #define RT1015_SYS_RST2 0x1009 114df310074SJack Yu #define RT1015_SYS_GATING1 0x100a 115df310074SJack Yu #define RT1015_TEST_MODE1 0x100c 116df310074SJack Yu #define RT1015_TEST_MODE2 0x100d 117df310074SJack Yu #define RT1015_TIMING_CTRL1 0x100e 118df310074SJack Yu #define RT1015_PLL_INT 0x1010 119df310074SJack Yu #define RT1015_TEST_OUT1 0x1020 120df310074SJack Yu #define RT1015_DC_CALIB_CLSD1 0x1200 121df310074SJack Yu #define RT1015_DC_CALIB_CLSD2 0x1202 122df310074SJack Yu #define RT1015_DC_CALIB_CLSD3 0x1204 123df310074SJack Yu #define RT1015_DC_CALIB_CLSD4 0x1206 124df310074SJack Yu #define RT1015_DC_CALIB_CLSD5 0x1208 125df310074SJack Yu #define RT1015_DC_CALIB_CLSD6 0x120a 126df310074SJack Yu #define RT1015_DC_CALIB_CLSD7 0x120c 127df310074SJack Yu #define RT1015_DC_CALIB_CLSD8 0x120e 128df310074SJack Yu #define RT1015_DC_CALIB_CLSD9 0x1210 129df310074SJack Yu #define RT1015_DC_CALIB_CLSD10 0x1212 130df310074SJack Yu #define RT1015_CLSD_INTERNAL1 0x1300 131df310074SJack Yu #define RT1015_CLSD_INTERNAL2 0x1302 132df310074SJack Yu #define RT1015_CLSD_INTERNAL3 0x1304 133df310074SJack Yu #define RT1015_CLSD_INTERNAL4 0x1305 134df310074SJack Yu #define RT1015_CLSD_INTERNAL5 0x1306 135df310074SJack Yu #define RT1015_CLSD_INTERNAL6 0x1308 136df310074SJack Yu #define RT1015_CLSD_INTERNAL7 0x130a 137df310074SJack Yu #define RT1015_CLSD_INTERNAL8 0x130c 138df310074SJack Yu #define RT1015_CLSD_INTERNAL9 0x130e 139df310074SJack Yu #define RT1015_CLSD_OCP_CTRL 0x130f 140df310074SJack Yu #define RT1015_VREF_LV 0x1310 141df310074SJack Yu #define RT1015_MBIAS1 0x1312 142df310074SJack Yu #define RT1015_MBIAS2 0x1314 143df310074SJack Yu #define RT1015_MBIAS3 0x1316 144df310074SJack Yu #define RT1015_MBIAS4 0x1318 145df310074SJack Yu #define RT1015_VREF_LV1 0x131a 146df310074SJack Yu #define RT1015_S_BST_TIMING_INTER1 0x1322 147df310074SJack Yu #define RT1015_S_BST_TIMING_INTER2 0x1323 148df310074SJack Yu #define RT1015_S_BST_TIMING_INTER3 0x1324 149df310074SJack Yu #define RT1015_S_BST_TIMING_INTER4 0x1325 150df310074SJack Yu #define RT1015_S_BST_TIMING_INTER5 0x1326 151df310074SJack Yu #define RT1015_S_BST_TIMING_INTER6 0x1327 152df310074SJack Yu #define RT1015_S_BST_TIMING_INTER7 0x1328 153df310074SJack Yu #define RT1015_S_BST_TIMING_INTER8 0x1329 154df310074SJack Yu #define RT1015_S_BST_TIMING_INTER9 0x132a 155df310074SJack Yu #define RT1015_S_BST_TIMING_INTER10 0x132b 156df310074SJack Yu #define RT1015_S_BST_TIMING_INTER11 0x1330 157df310074SJack Yu #define RT1015_S_BST_TIMING_INTER12 0x1331 158df310074SJack Yu #define RT1015_S_BST_TIMING_INTER13 0x1332 159df310074SJack Yu #define RT1015_S_BST_TIMING_INTER14 0x1333 160df310074SJack Yu #define RT1015_S_BST_TIMING_INTER15 0x1334 161df310074SJack Yu #define RT1015_S_BST_TIMING_INTER16 0x1335 162df310074SJack Yu #define RT1015_S_BST_TIMING_INTER17 0x1336 163df310074SJack Yu #define RT1015_S_BST_TIMING_INTER18 0x1337 164df310074SJack Yu #define RT1015_S_BST_TIMING_INTER19 0x1338 165df310074SJack Yu #define RT1015_S_BST_TIMING_INTER20 0x1339 166df310074SJack Yu #define RT1015_S_BST_TIMING_INTER21 0x133a 167df310074SJack Yu #define RT1015_S_BST_TIMING_INTER22 0x133b 168df310074SJack Yu #define RT1015_S_BST_TIMING_INTER23 0x133c 169df310074SJack Yu #define RT1015_S_BST_TIMING_INTER24 0x133d 170df310074SJack Yu #define RT1015_S_BST_TIMING_INTER25 0x133e 171df310074SJack Yu #define RT1015_S_BST_TIMING_INTER26 0x133f 172df310074SJack Yu #define RT1015_S_BST_TIMING_INTER27 0x1340 173df310074SJack Yu #define RT1015_S_BST_TIMING_INTER28 0x1341 174df310074SJack Yu #define RT1015_S_BST_TIMING_INTER29 0x1342 175df310074SJack Yu #define RT1015_S_BST_TIMING_INTER30 0x1343 176df310074SJack Yu #define RT1015_S_BST_TIMING_INTER31 0x1344 177df310074SJack Yu #define RT1015_S_BST_TIMING_INTER32 0x1345 178df310074SJack Yu #define RT1015_S_BST_TIMING_INTER33 0x1346 179df310074SJack Yu #define RT1015_S_BST_TIMING_INTER34 0x1347 180df310074SJack Yu #define RT1015_S_BST_TIMING_INTER35 0x1348 181df310074SJack Yu #define RT1015_S_BST_TIMING_INTER36 0x1349 182df310074SJack Yu 183df310074SJack Yu /* 0x0004 */ 184df310074SJack Yu #define RT1015_CLK_SYS_PRE_SEL_MASK (0x3 << 14) 185df310074SJack Yu #define RT1015_CLK_SYS_PRE_SEL_SFT 14 186df310074SJack Yu #define RT1015_CLK_SYS_PRE_SEL_MCLK (0x0 << 14) 187df310074SJack Yu #define RT1015_CLK_SYS_PRE_SEL_PLL (0x2 << 14) 188df310074SJack Yu #define RT1015_PLL_SEL_MASK (0x1 << 13) 189df310074SJack Yu #define RT1015_PLL_SEL_SFT 13 190df310074SJack Yu #define RT1015_PLL_SEL_PLL_SRC2 (0x0 << 13) 191df310074SJack Yu #define RT1015_PLL_SEL_BCLK (0x1 << 13) 192df310074SJack Yu #define RT1015_FS_PD_MASK (0x7 << 4) 193df310074SJack Yu #define RT1015_FS_PD_SFT 4 194df310074SJack Yu 195df310074SJack Yu /* 0x000a */ 196df310074SJack Yu #define RT1015_PLL_M_MAX 0xf 197df310074SJack Yu #define RT1015_PLL_M_MASK (RT1015_PLL_M_MAX << 12) 198df310074SJack Yu #define RT1015_PLL_M_SFT 12 199df310074SJack Yu #define RT1015_PLL_M_BP (0x1 << 11) 200df310074SJack Yu #define RT1015_PLL_M_BP_SFT 11 201df310074SJack Yu #define RT1015_PLL_N_MAX 0x1ff 202df310074SJack Yu #define RT1015_PLL_N_MASK (RT1015_PLL_N_MAX << 0) 203df310074SJack Yu #define RT1015_PLL_N_SFT 0 204df310074SJack Yu 205df310074SJack Yu /* 0x000c */ 206df310074SJack Yu #define RT1015_PLL_BPK_MASK (0x1 << 5) 207df310074SJack Yu #define RT1015_PLL_BPK (0x0 << 5) 208df310074SJack Yu #define RT1015_PLL_K_MAX 0x1f 209df310074SJack Yu #define RT1015_PLL_K_MASK (RT1015_PLL_K_MAX) 210df310074SJack Yu #define RT1015_PLL_K_SFT 0 211df310074SJack Yu 212*9f44673bSJack Yu /* 0x0020 */ 213*9f44673bSJack Yu #define RT1015_EN_BCLK_DET_MASK (0x1 << 15) 214*9f44673bSJack Yu #define RT1015_EN_BCLK_DET (0x1 << 15) 215*9f44673bSJack Yu #define RT1015_DIS_BCLK_DET (0x0 << 15) 216*9f44673bSJack Yu 217df310074SJack Yu /* 0x007a */ 218df310074SJack Yu #define RT1015_ID_MASK 0xff 219df310074SJack Yu #define RT1015_ID_VERA 0x0 220df310074SJack Yu #define RT1015_ID_VERB 0x1 221df310074SJack Yu 2227e9a2387SShuming Fan /* 0x00f2 */ 2237e9a2387SShuming Fan #define RT1015_MONO_LR_SEL_MASK (0x3 << 4) 2247e9a2387SShuming Fan #define RT1015_MONO_L_CHANNEL (0x0 << 4) 2257e9a2387SShuming Fan #define RT1015_MONO_R_CHANNEL (0x1 << 4) 2267e9a2387SShuming Fan #define RT1015_MONO_LR_MIX_CHANNEL (0x2 << 4) 2277e9a2387SShuming Fan 228df310074SJack Yu /* 0x0102 */ 229df310074SJack Yu #define RT1015_DAC_VOL_MASK (0x7f << 9) 230df310074SJack Yu #define RT1015_DAC_VOL_SFT 9 231df310074SJack Yu 232df310074SJack Yu /* 0x0104 */ 233df310074SJack Yu #define RT1015_DAC_CLK (0x1 << 13) 234df310074SJack Yu #define RT1015_DAC_CLK_BIT 13 235df310074SJack Yu 236df310074SJack Yu /* 0x0106 */ 237df310074SJack Yu #define RT1015_DAC_MUTE_MASK (0x1 << 15) 238df310074SJack Yu #define RT1015_DA_MUTE_SFT 15 239df310074SJack Yu #define RT1015_DVOL_MUTE_FLAG_SFT 12 240df310074SJack Yu 241df310074SJack Yu /* 0x0111 */ 242df310074SJack Yu #define RT1015_TCON_TDM_MS_MASK (0x1 << 14) 243df310074SJack Yu #define RT1015_TCON_TDM_MS_SFT 14 244df310074SJack Yu #define RT1015_TCON_TDM_MS_S (0x0 << 14) 245df310074SJack Yu #define RT1015_TCON_TDM_MS_M (0x1 << 14) 246df310074SJack Yu #define RT1015_I2S_DL_MASK (0x7 << 8) 247df310074SJack Yu #define RT1015_I2S_DL_SFT 8 248df310074SJack Yu #define RT1015_I2S_DL_16 (0x0 << 8) 249df310074SJack Yu #define RT1015_I2S_DL_20 (0x1 << 8) 250df310074SJack Yu #define RT1015_I2S_DL_24 (0x2 << 8) 251df310074SJack Yu #define RT1015_I2S_DL_8 (0x3 << 8) 252df310074SJack Yu #define RT1015_I2S_M_DF_MASK (0x7 << 0) 253df310074SJack Yu #define RT1015_I2S_M_DF_SFT 0 254df310074SJack Yu #define RT1015_I2S_M_DF_I2S (0x0) 255df310074SJack Yu #define RT1015_I2S_M_DF_LEFT (0x1) 256df310074SJack Yu #define RT1015_I2S_M_DF_PCM_A (0x2) 257df310074SJack Yu #define RT1015_I2S_M_DF_PCM_B (0x3) 258df310074SJack Yu #define RT1015_I2S_M_DF_PCM_A_N (0x6) 259df310074SJack Yu #define RT1015_I2S_M_DF_PCM_B_N (0x7) 260df310074SJack Yu 261df310074SJack Yu /* TDM_tcon Setting (0x0112) */ 262df310074SJack Yu #define RT1015_I2S_TCON_DF_MASK (0x7 << 13) 263df310074SJack Yu #define RT1015_I2S_TCON_DF_SFT 13 264df310074SJack Yu #define RT1015_I2S_TCON_DF_I2S (0x0 << 13) 265df310074SJack Yu #define RT1015_I2S_TCON_DF_LEFT (0x1 << 13) 266df310074SJack Yu #define RT1015_I2S_TCON_DF_PCM_A (0x2 << 13) 267df310074SJack Yu #define RT1015_I2S_TCON_DF_PCM_B (0x3 << 13) 268df310074SJack Yu #define RT1015_I2S_TCON_DF_PCM_A_N (0x6 << 13) 269df310074SJack Yu #define RT1015_I2S_TCON_DF_PCM_B_N (0x7 << 13) 270df310074SJack Yu #define RT1015_TCON_BCLK_SEL_MASK (0x3 << 10) 271df310074SJack Yu #define RT1015_TCON_BCLK_SEL_SFT 10 272df310074SJack Yu #define RT1015_TCON_BCLK_SEL_32FS (0x0 << 10) 273df310074SJack Yu #define RT1015_TCON_BCLK_SEL_64FS (0x1 << 10) 274df310074SJack Yu #define RT1015_TCON_BCLK_SEL_128FS (0x2 << 10) 275df310074SJack Yu #define RT1015_TCON_BCLK_SEL_256FS (0x3 << 10) 276df310074SJack Yu #define RT1015_TCON_CH_LEN_MASK (0x3 << 5) 277df310074SJack Yu #define RT1015_TCON_CH_LEN_SFT 5 278df310074SJack Yu #define RT1015_TCON_CH_LEN_16B (0x0 << 5) 279df310074SJack Yu #define RT1015_TCON_CH_LEN_20B (0x1 << 5) 280df310074SJack Yu #define RT1015_TCON_CH_LEN_24B (0x2 << 5) 281df310074SJack Yu #define RT1015_TCON_CH_LEN_32B (0x3 << 5) 282df310074SJack Yu #define RT1015_TCON_BCLK_MST_MASK (0x1 << 4) 283df310074SJack Yu #define RT1015_TCON_BCLK_MST_SFT 4 284df310074SJack Yu #define RT1015_TCON_BCLK_MST_INV (0x1 << 4) 285df310074SJack Yu 286df310074SJack Yu /* TDM1 Setting-1 (0x0114) */ 287df310074SJack Yu #define RT1015_TDM_INV_BCLK_MASK (0x1 << 15) 288df310074SJack Yu #define RT1015_TDM_INV_BCLK_SFT 15 289df310074SJack Yu #define RT1015_TDM_INV_BCLK (0x1 << 15) 2907e9a2387SShuming Fan #define RT1015_I2S_CH_TX_MASK (0x3 << 10) 2917e9a2387SShuming Fan #define RT1015_I2S_CH_TX_SFT 10 2927e9a2387SShuming Fan #define RT1015_I2S_TX_2CH (0x0 << 10) 2937e9a2387SShuming Fan #define RT1015_I2S_TX_4CH (0x1 << 10) 2947e9a2387SShuming Fan #define RT1015_I2S_TX_6CH (0x2 << 10) 2957e9a2387SShuming Fan #define RT1015_I2S_TX_8CH (0x3 << 10) 2967e9a2387SShuming Fan #define RT1015_I2S_CH_RX_MASK (0x3 << 8) 2977e9a2387SShuming Fan #define RT1015_I2S_CH_RX_SFT 8 2987e9a2387SShuming Fan #define RT1015_I2S_RX_2CH (0x0 << 8) 2997e9a2387SShuming Fan #define RT1015_I2S_RX_4CH (0x1 << 8) 3007e9a2387SShuming Fan #define RT1015_I2S_RX_6CH (0x2 << 8) 3017e9a2387SShuming Fan #define RT1015_I2S_RX_8CH (0x3 << 8) 3027e9a2387SShuming Fan #define RT1015_I2S_LR_CH_SEL_MASK (0x1 << 7) 3037e9a2387SShuming Fan #define RT1015_I2S_LR_CH_SEL_SFT 7 3047e9a2387SShuming Fan #define RT1015_I2S_LEFT_CH_SEL (0x0 << 7) 3057e9a2387SShuming Fan #define RT1015_I2S_RIGHT_CH_SEL (0x1 << 7) 3067e9a2387SShuming Fan #define RT1015_I2S_CH_TX_LEN_MASK (0x7 << 4) 3077e9a2387SShuming Fan #define RT1015_I2S_CH_TX_LEN_SFT 4 3087e9a2387SShuming Fan #define RT1015_I2S_CH_TX_LEN_16B (0x0 << 4) 3097e9a2387SShuming Fan #define RT1015_I2S_CH_TX_LEN_20B (0x1 << 4) 3107e9a2387SShuming Fan #define RT1015_I2S_CH_TX_LEN_24B (0x2 << 4) 3117e9a2387SShuming Fan #define RT1015_I2S_CH_TX_LEN_32B (0x3 << 4) 3127e9a2387SShuming Fan #define RT1015_I2S_CH_TX_LEN_8B (0x4 << 4) 3137e9a2387SShuming Fan #define RT1015_I2S_CH_RX_LEN_MASK (0x7 << 0) 3147e9a2387SShuming Fan #define RT1015_I2S_CH_RX_LEN_SFT 0 3157e9a2387SShuming Fan #define RT1015_I2S_CH_RX_LEN_16B (0x0 << 0) 3167e9a2387SShuming Fan #define RT1015_I2S_CH_RX_LEN_20B (0x1 << 0) 3177e9a2387SShuming Fan #define RT1015_I2S_CH_RX_LEN_24B (0x2 << 0) 3187e9a2387SShuming Fan #define RT1015_I2S_CH_RX_LEN_32B (0x3 << 0) 3197e9a2387SShuming Fan #define RT1015_I2S_CH_RX_LEN_8B (0x4 << 0) 3207e9a2387SShuming Fan 3217e9a2387SShuming Fan /* TDM1 Setting-4 (0x011a) */ 3227e9a2387SShuming Fan #define RT1015_TDM_I2S_TX_L_DAC1_1_MASK (0x7 << 12) 3237e9a2387SShuming Fan #define RT1015_TDM_I2S_TX_R_DAC1_1_MASK (0x7 << 8) 3247e9a2387SShuming Fan #define RT1015_TDM_I2S_TX_L_DAC1_1_SFT 12 3257e9a2387SShuming Fan #define RT1015_TDM_I2S_TX_R_DAC1_1_SFT 8 326df310074SJack Yu 327df310074SJack Yu /* 0x0330 */ 328df310074SJack Yu #define RT1015_ABST_AUTO_EN_MASK (0x1 << 13) 329df310074SJack Yu #define RT1015_ABST_AUTO_MODE (0x1 << 13) 330df310074SJack Yu #define RT1015_ABST_REG_MODE (0x0 << 13) 331df310074SJack Yu #define RT1015_ABST_FIX_TGT_MASK (0x1 << 12) 332df310074SJack Yu #define RT1015_ABST_FIX_TGT_EN (0x1 << 12) 333df310074SJack Yu #define RT1015_ABST_FIX_TGT_DIS (0x0 << 12) 334df310074SJack Yu #define RT1015_BYPASS_SWR_REG_MASK (0x1 << 7) 335df310074SJack Yu #define RT1015_BYPASS_SWRREG_BYPASS (0x1 << 7) 336df310074SJack Yu #define RT1015_BYPASS_SWRREG_PASS (0x0 << 7) 337df310074SJack Yu 338df310074SJack Yu /* 0x0322 */ 339df310074SJack Yu #define RT1015_PWR_LDO2 (0x1 << 15) 340df310074SJack Yu #define RT1015_PWR_LDO2_BIT 15 341df310074SJack Yu #define RT1015_PWR_DAC (0x1 << 14) 342df310074SJack Yu #define RT1015_PWR_DAC_BIT 14 343df310074SJack Yu #define RT1015_PWR_INTCLK (0x1 << 13) 344df310074SJack Yu #define RT1015_PWR_INTCLK_BIT 13 345df310074SJack Yu #define RT1015_PWR_ISENSE (0x1 << 12) 346df310074SJack Yu #define RT1015_PWR_ISENSE_BIT 12 347df310074SJack Yu #define RT1015_PWR_VSENSE (0x1 << 10) 348df310074SJack Yu #define RT1015_PWR_VSENSE_BIT 10 349df310074SJack Yu #define RT1015_PWR_PLL (0x1 << 9) 350df310074SJack Yu #define RT1015_PWR_PLL_BIT 9 351df310074SJack Yu #define RT1015_PWR_BG_1_2 (0x1 << 8) 352df310074SJack Yu #define RT1015_PWR_BG_1_2_BIT 8 353df310074SJack Yu #define RT1015_PWR_MBIAS_BG (0x1 << 7) 354df310074SJack Yu #define RT1015_PWR_MBIAS_BG_BIT 7 355df310074SJack Yu #define RT1015_PWR_VBAT (0x1 << 6) 356df310074SJack Yu #define RT1015_PWR_VBAT_BIT 6 357df310074SJack Yu #define RT1015_PWR_MBIAS (0x1 << 4) 358df310074SJack Yu #define RT1015_PWR_MBIAS_BIT 4 359df310074SJack Yu #define RT1015_PWR_ADCV (0x1 << 3) 360df310074SJack Yu #define RT1015_PWR_ADCV_BIT 3 361df310074SJack Yu #define RT1015_PWR_MIXERV (0x1 << 2) 362df310074SJack Yu #define RT1015_PWR_MIXERV_BIT 2 363df310074SJack Yu #define RT1015_PWR_SUMV (0x1 << 1) 364df310074SJack Yu #define RT1015_PWR_SUMV_BIT 1 365df310074SJack Yu #define RT1015_PWR_VREFLV (0x1 << 0) 366df310074SJack Yu #define RT1015_PWR_VREFLV_BIT 0 367df310074SJack Yu 368df310074SJack Yu /* 0x0324 */ 369df310074SJack Yu #define RT1015_PWR_BASIC (0x1 << 15) 370df310074SJack Yu #define RT1015_PWR_BASIC_BIT 15 371df310074SJack Yu #define RT1015_PWR_SD (0x1 << 14) 372df310074SJack Yu #define RT1015_PWR_SD_BIT 14 373df310074SJack Yu #define RT1015_PWR_IBIAS (0x1 << 13) 374df310074SJack Yu #define RT1015_PWR_IBIAS_BIT 13 375df310074SJack Yu #define RT1015_PWR_VCM (0x1 << 11) 376df310074SJack Yu #define RT1015_PWR_VCM_BIT 11 377df310074SJack Yu 378df310074SJack Yu /* 0x0328 */ 379df310074SJack Yu #define RT1015_PWR_SWR (0x1 << 12) 380df310074SJack Yu #define RT1015_PWR_SWR_BIT 12 381df310074SJack Yu 382*9f44673bSJack Yu /* 0x0519 */ 383*9f44673bSJack Yu #define RT1015_EN_CLA_D_DC_DET_MASK (0x1 << 12) 384*9f44673bSJack Yu #define RT1015_EN_CLA_D_DC_DET (0x1 << 12) 385*9f44673bSJack Yu #define RT1015_DIS_CLA_D_DC_DET (0x0 << 12) 386*9f44673bSJack Yu 387df310074SJack Yu /* 0x1300 */ 388df310074SJack Yu #define RT1015_PWR_CLSD (0x1 << 12) 389df310074SJack Yu #define RT1015_PWR_CLSD_BIT 12 390df310074SJack Yu 391df310074SJack Yu /* 0x007a */ 392df310074SJack Yu #define RT1015_ID_MASK 0xff 393df310074SJack Yu #define RT1015_ID_VERA 0x0 394df310074SJack Yu #define RT1015_ID_VERB 0x1 395df310074SJack Yu 396df310074SJack Yu /* System Clock Source */ 397df310074SJack Yu enum { 398df310074SJack Yu RT1015_SCLK_S_MCLK, 399df310074SJack Yu RT1015_SCLK_S_PLL, 400df310074SJack Yu }; 401df310074SJack Yu 402df310074SJack Yu /* PLL1 Source */ 403df310074SJack Yu enum { 404df310074SJack Yu RT1015_PLL_S_MCLK, 405df310074SJack Yu RT1015_PLL_S_BCLK, 406df310074SJack Yu }; 407df310074SJack Yu 408df310074SJack Yu enum { 409df310074SJack Yu RT1015_AIF1, 410df310074SJack Yu RT1015_AIFS, 411df310074SJack Yu }; 412df310074SJack Yu 413df310074SJack Yu enum { 414df310074SJack Yu RT1015_VERA, 415df310074SJack Yu RT1015_VERB, 416df310074SJack Yu }; 417df310074SJack Yu 418df310074SJack Yu enum { 419df310074SJack Yu BYPASS, 420df310074SJack Yu ADAPTIVE, 421df310074SJack Yu FIXED_ADAPTIVE, 422df310074SJack Yu }; 423df310074SJack Yu 424668b1508SJack Yu enum { 425668b1508SJack Yu RT1015_Enable_Boost = 0, 426668b1508SJack Yu RT1015_Bypass_Boost, 427668b1508SJack Yu }; 428668b1508SJack Yu 4298d9a14fcSderek.fang enum { 4308d9a14fcSderek.fang RT1015_HW_28 = 0, 4318d9a14fcSderek.fang RT1015_HW_29, 4328d9a14fcSderek.fang }; 4338d9a14fcSderek.fang 434df310074SJack Yu struct rt1015_priv { 435df310074SJack Yu struct snd_soc_component *component; 43693bd813cSJack Yu struct rt1015_platform_data pdata; 437df310074SJack Yu struct regmap *regmap; 438df310074SJack Yu int sysclk; 439df310074SJack Yu int sysclk_src; 440df310074SJack Yu int pll_src; 441df310074SJack Yu int pll_in; 442df310074SJack Yu int pll_out; 443df310074SJack Yu int boost_mode; 444df310074SJack Yu int bypass_boost; 445df310074SJack Yu int dac_is_used; 446da145172Sderek.fang int cali_done; 447df310074SJack Yu }; 448df310074SJack Yu 449df310074SJack Yu #endif /* __RT1015_H__ */ 450