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12

/openbmc/openpower-pnor-code-mgmt/test/
H A Dtest_item_updater_static.cpp22 "TOC@0x00000000 Partitions:\n" in TEST()
24 "ID=00 part 0x00000000..0x00002000 (actual=0x00002000) " in TEST()
26 "ID=01 HBEL 0x00008000..0x0002c000 (actual=0x00024000) " in TEST()
28 "ID=02 GUARD 0x0002c000..0x00031000 (actual=0x00005000) " in TEST()
30 "ID=03 NVRAM 0x00031000..0x000c1000 (actual=0x00090000) " in TEST()
32 "ID=04 SECBOOT 0x000c1000..0x000e5000 (actual=0x00024000) " in TEST()
34 "ID=05 DJVPD 0x000e5000..0x0012d000 (actual=0x00048000) " in TEST()
36 "ID=06 MVPD 0x0012d000..0x001bd000 (actual=0x00090000) " in TEST()
38 "ID=07 CVPD 0x001bd000..0x00205000 (actual=0x00048000) " in TEST()
40 "ID=08 HBB 0x00205000..0x00305000 (actual=0x00100000) " in TEST()
[all …]
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-tf300t.dts75 reg = <0x10>;
94 mount-matrix = "0", "-1", "0",
95 "-1", "0", "0",
96 "0", "0", "-1";
100 mount-matrix = "-1", "0", "0",
101 "0", "1", "0",
102 "0", "0", "-1";
107 mount-matrix = "0", "-1", "0",
108 "-1", "0", "0",
109 "0", "0", "1";
[all …]
H A Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi13 emc-timings-0 {
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
19 nvidia,emc-mode-2 = <0x80200018>;
20 nvidia,emc-mode-reset = <0x80000b71>;
21 nvidia,emc-zcal-cnt-long = <0x00000040>;
25 0x0000001f /* EMC_RC */
26 0x00000069 /* EMC_RFC */
27 0x00000017 /* EMC_RAS */
28 0x00000007 /* EMC_RP */
[all …]
H A Dtegra30-asus-tf700t.dts18 port@0 {
92 reg = <0x10>;
111 mount-matrix = "1", "0", "0",
112 "0", "-1", "0",
113 "0", "0", "-1";
117 mount-matrix = "0", "1", "0",
118 "1", "0", "0",
119 "0", "0", "-1";
124 mount-matrix = "0", "-1", "0",
125 "-1", "0", "0",
[all …]
H A Dtegra30-asus-tf201.dts67 reg = <0x4d>;
82 mount-matrix = "-1", "0", "0",
83 "0", "-1", "0",
84 "0", "0", "-1";
88 mount-matrix = "0", "-1", "0",
89 "-1", "0", "0",
90 "0", "0", "-1";
95 mount-matrix = "1", "0", "0",
96 "0", "-1", "0",
97 "0", "0", "1";
[all …]
H A Dtegra30-asus-nexus7-grouper-memory-timings.dtsi5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
12 0x00020001 /* MC_EMEM_ARB_CFG */
13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
19 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
[all …]
H A Dtegra124-nyan-big-emc.dtsi263 0x40040001 /* MC_EMEM_ARB_CFG */
264 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
265 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
266 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
267 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
268 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
269 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
270 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
271 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
272 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi104 0x40040001
105 0x8000000a
106 0x00000001
107 0x00000001
108 0x00000002
109 0x00000000
110 0x00000002
111 0x00000001
112 0x00000003
113 0x00000008
[all …]
H A Dtegra124-apalis-emc.dtsi108 0x40040001 0x8000000a
109 0x00000001 0x00000001
110 0x00000002 0x00000000
111 0x00000002 0x00000001
112 0x00000003 0x00000008
113 0x00000003 0x00000002
114 0x00000003 0x00000006
115 0x06030203 0x000a0502
116 0x77e30303 0x70000f03
117 0x001f0000
[all …]
H A Dtegra30-asus-tf300tg.dts22 <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>,
171 reg = <0x10>;
190 mount-matrix = "1", "0", "0",
191 "0", "-1", "0",
192 "0", "0", "-1";
196 mount-matrix = "-1", "0", "0",
197 "0", "1", "0",
198 "0", "0", "-1";
203 mount-matrix = "0", "-1", "0",
204 "-1", "0", "0",
[all …]
H A Dtegra30-ouya.dts32 tlm,version-major = <0x0>;
33 tlm,version-minor = <0x0>;
38 reg = <0x80000000 0x40000000>;
48 alloc-ranges = <0x80000000 0x30000000>;
49 size = <0x10000000>; /* 256MiB */
56 reg = <0xbfdf0000 0x10000>; /* 64kB */
57 console-size = <0x8000>; /* 32kB */
58 record-size = <0x400>; /* 1kB */
63 reg = <0xbfe00000 0x200000>;
81 pinctrl-0 = <&state_default>;
[all …]
H A Dtegra30-pegatron-chagall.dts49 reg = <0x80000000 0x40000000>;
59 alloc-ranges = <0x80000000 0x30000000>;
60 size = <0x10000000>; /* 256MiB */
67 reg = <0xbeb00000 0x10000>; /* 64kB */
68 console-size = <0x8000>; /* 32kB */
69 record-size = <0x400>; /* 1kB */
74 reg = <0xbfe00000 0x200000>; /* 2MB */
100 pinctrl-0 = <&state_default>;
144 nvidia,lock = <0>;
145 nvidia,io-reset = <0>;
[all …]
/openbmc/u-boot/board/micronas/vct/vctv/
H A Dreg_gpio.h6 #define GPIO1_BASE 0x00044000
7 #define GPIO2_BASE 0x00048000
13 #define GPIO_SWPORTA_DR_OFFS 0x00000000
15 #define GPIO_SWPORTA_DDR_OFFS 0x00000004
17 #define GPIO_EXT_PORTA_OFFS 0x00000050
/openbmc/linux/drivers/gpu/drm/gma500/
H A Dpsb_reg.h13 #define PSB_CR_CLKGATECTL 0x0000
16 #define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
18 #define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
20 #define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
22 #define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
24 #define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
25 #define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
26 #define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
27 #define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
31 #define PSB_CR_CORE_ID 0x0010
[all …]
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,k3-dsp-rproc.yaml148 mailbox0_cluster3: mailbox-0 {
160 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
161 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71_0 */
162 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
163 <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>; /* C66_1 */
168 reg = <0x4d 0x80800000 0x00 0x00048000>,
169 <0x4d 0x80e00000 0x00 0x00008000>,
170 <0x4d 0x80f00000 0x00 0x00008000>;
174 ti,sci-proc-ids = <0x03 0xFF>;
185 reg = <0x00 0x64800000 0x00 0x00080000>,
[all …]
/openbmc/u-boot/arch/m68k/include/asm/
H A Dimmap_520x.h12 #define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000)
13 #define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000)
14 #define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000)
15 #define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000)
16 #define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000)
17 #define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000)
18 #define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000)
19 #define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000)
20 #define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000)
21 #define MMAP_QSPI (CONFIG_SYS_MBAR + 0x0005C000)
[all …]
H A Dimmap_5227x.h13 #define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000)
14 #define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000)
15 #define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000)
16 #define MMAP_CAN (CONFIG_SYS_MBAR + 0x00020000)
17 #define MMAP_RTC (CONFIG_SYS_MBAR + 0x0003C000)
18 #define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040010)
19 #define MMAP_SCM3 (CONFIG_SYS_MBAR + 0x00040070)
20 #define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000)
21 #define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000)
22 #define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000)
[all …]
H A Dimmap_5301x.h12 #define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000)
13 #define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000)
14 #define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000)
15 #define MMAP_MPU (CONFIG_SYS_MBAR + 0x00014000)
16 #define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000)
17 #define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00034000)
18 #define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000)
19 #define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000)
20 #define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000)
21 #define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000)
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A Drtl8xxxu_8710b.c34 {0x421, 0x0F}, {0x428, 0x0A}, {0x429, 0x10}, {0x430, 0x00},
35 {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04},
36 {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, {0x43C, 0x04},
37 {0x43D, 0x05}, {0x43E, 0x07}, {0x43F, 0x08}, {0x440, 0x5D},
38 {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00},
39 {0x446, 0x00}, {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xF0},
40 {0x44A, 0x0F}, {0x44B, 0x3E}, {0x44C, 0x10}, {0x44D, 0x00},
41 {0x44E, 0x00}, {0x44F, 0x00}, {0x450, 0x00}, {0x451, 0xF0},
42 {0x452, 0x0F}, {0x453, 0x00}, {0x456, 0x5E}, {0x460, 0x66},
43 {0x461, 0x66}, {0x4C8, 0xFF}, {0x4C9, 0x08}, {0x4CC, 0xFF},
[all …]
H A Drtl8xxxu_8188f.c34 {0x024, 0xDF}, {0x025, 0x07}, {0x02B, 0x1C}, {0x283, 0x20},
35 {0x421, 0x0F}, {0x428, 0x0A}, {0x429, 0x10}, {0x430, 0x00},
36 {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04},
37 {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, {0x43C, 0x04},
38 {0x43D, 0x05}, {0x43E, 0x07}, {0x43F, 0x08}, {0x440, 0x5D},
39 {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00},
40 {0x446, 0x00}, {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xF0},
41 {0x44A, 0x0F}, {0x44B, 0x3E}, {0x44C, 0x10}, {0x44D, 0x00},
42 {0x44E, 0x00}, {0x44F, 0x00}, {0x450, 0x00}, {0x451, 0xF0},
43 {0x452, 0x0F}, {0x453, 0x00}, {0x456, 0x5E}, {0x460, 0x44},
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dimx-regs.h11 #define IRAM_BASE_ADDR 0x3E800000 /* internal ram */
12 #define IRAM_SIZE 0x00400000 /* 4MB */
14 #define AIPS0_BASE_ADDR (0x40000000UL)
15 #define AIPS1_BASE_ADDR (0x40080000UL)
17 /* AIPS 0 */
18 #define AXBS_BASE_ADDR (AIPS0_BASE_ADDR + 0x00000000)
19 #define CSE3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000)
20 #define EDMA_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000)
21 #define XRDC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00004000)
22 #define SWT0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000)
[all …]
/openbmc/u-boot/drivers/video/
H A Dipu_regs.h16 #define IPU_DISP0_BASE 0x00000000
19 #define IPU_CM_REG_BASE 0x00000000
20 #define IPU_STAT_REG_BASE 0x00000200
21 #define IPU_IDMAC_REG_BASE 0x00008000
22 #define IPU_ISP_REG_BASE 0x00010000
23 #define IPU_DP_REG_BASE 0x00018000
24 #define IPU_IC_REG_BASE 0x00020000
25 #define IPU_IRT_REG_BASE 0x00028000
26 #define IPU_CSI0_REG_BASE 0x00030000
27 #define IPU_CSI1_REG_BASE 0x00038000
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
H A Dtable.c6 0x800, 0x80040000,
7 0x804, 0x00000003,
8 0x808, 0x0000FC00,
9 0x80C, 0x0000000A,
10 0x810, 0x10001331,
11 0x814, 0x020C3D10,
12 0x818, 0x02220385,
13 0x81C, 0x00000000,
14 0x820, 0x01000100,
15 0x824, 0x00390204,
[all …]
/openbmc/linux/drivers/video/fbdev/nvidia/
H A Dnv_accel.c65 0xCC, /* copy */
66 0x55 /* invert */
70 0xCA, /* copy */
71 0x5A, /* invert */
101 while (--count && NV_RD32(par->PGRAPH, 0x0700)) ; in NVSync()
130 NVDmaNext(par, 0x20000000); in NVDmaWait()
173 if (planemask != ~0) { in NVSetRopSolid()
174 NVSetPattern(info, 0, planemask, ~0, ~0); in NVSetRopSolid()
182 NVSetPattern(info, ~0, ~0, ~0, ~0); in NVSetRopSolid()
211 for (i = 0; i < SKIPS; i++) in NVResetGraphics()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-vf610/
H A Dimx-regs.h11 #define IRAM_BASE_ADDR 0x3F000000 /* internal ram */
12 #define IRAM_SIZE 0x00080000 /* 512 KB */
14 #define AIPS0_BASE_ADDR 0x40000000
15 #define AIPS1_BASE_ADDR 0x40080000
17 /* AIPS 0 */
18 #define MSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000)
19 #define MSCM_IR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001800)
20 #define CA5SCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000)
21 #define CA5_INTD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00003000)
22 #define CA5_L2C_BASE_ADDR (AIPS0_BASE_ADDR + 0x00006000)
[all …]

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