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/openbmc/linux/tools/perf/pmu-events/arch/riscv/sifive/u74/
H A Dinstructions.json4 "EventCode": "0x0000100",
9 "EventCode": "0x0000200",
14 "EventCode": "0x0000400",
19 "EventCode": "0x0000800",
24 "EventCode": "0x0001000",
29 "EventCode": "0x0002000",
34 "EventCode": "0x0004000",
39 "EventCode": "0x0008000",
44 "EventCode": "0x0010000",
49 "EventCode": "0x0020000",
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Dffb.c65 #define FFB_SFB8R_VOFF 0x00000000
66 #define FFB_SFB8G_VOFF 0x00400000
67 #define FFB_SFB8B_VOFF 0x00800000
68 #define FFB_SFB8X_VOFF 0x00c00000
69 #define FFB_SFB32_VOFF 0x01000000
70 #define FFB_SFB64_VOFF 0x02000000
71 #define FFB_FBC_REGS_VOFF 0x04000000
72 #define FFB_BM_FBC_REGS_VOFF 0x04002000
73 #define FFB_DFB8R_VOFF 0x04004000
74 #define FFB_DFB8G_VOFF 0x04404000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dsnps,dw-wdt.yaml69 default: [0x0001000 0x0002000 0x0004000 0x0008000
70 0x0010000 0x0020000 0x0040000 0x0080000
71 0x0100000 0x0200000 0x0400000 0x0800000
72 0x1000000 0x2000000 0x4000000 0x8000000]
87 reg = <0xffd02000 0x1000>;
88 interrupts = <0 171 4>;
96 reg = <0xffd02000 0x1000>;
97 interrupts = <0 171 4>;
100 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
101 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dsnps,dw-pcie.yaml55 CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region
62 by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of
72 can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can
83 normally mapped to the 0x0 address of this region, while eDMA
84 is available at 0x80000 base address.
149 pattern: '^dma([0-9]|1[0-5])?$'
222 reg = <0xdfc00000 0x0001000>, /* IP registers */
223 <0xd0000000 0x0002000>; /* Configuration space */
227 ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
228 <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
[all …]
/openbmc/linux/include/sound/
H A Dacp63_chip_offset_byte.h12 #define ACP_DMA_CNTL_0 0x0000000
13 #define ACP_DMA_CNTL_1 0x0000004
14 #define ACP_DMA_CNTL_2 0x0000008
15 #define ACP_DMA_CNTL_3 0x000000C
16 #define ACP_DMA_CNTL_4 0x0000010
17 #define ACP_DMA_CNTL_5 0x0000014
18 #define ACP_DMA_CNTL_6 0x0000018
19 #define ACP_DMA_CNTL_7 0x000001C
20 #define ACP_DMA_DSCR_STRT_IDX_0 0x0000020
21 #define ACP_DMA_DSCR_STRT_IDX_1 0x0000024
[all …]
/openbmc/linux/drivers/media/pci/ivtv/
H A Divtvfb.c65 "Only use framebuffer of the specified ivtv card (0-31)\n"
77 Why start at 1 for left & upper coordinate ? Because X doesn't allow 0 */
91 "\t\t\tdefault 0 (Centered)");
95 "\t\t\tdefault 0 (Centered)");
111 #define IVTVFB_DBGFLG_WARN (1 << 0)
118 } while (0)
132 #define IVTV_OSD_BPP_8 0x00
133 #define IVTV_OSD_BPP_16_444 0x03
134 #define IVTV_OSD_BPP_16_555 0x02
135 #define IVTV_OSD_BPP_16_565 0x01
[all …]
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dg4x_dp.c47 { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
48 { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
53 return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0]; in vlv_get_dpll()
61 int i, count = 0; in g4x_dp_set_clock()
78 for (i = 0; i < count; i++) { in g4x_dp_set_clock()
145 TRANS_DP_ENH_FRAMING : 0); in intel_dp_prepare()
337 u32 tmp, flags = 0; in intel_dp_get_config()
419 DP_PORT_EN) == 0)) in intel_dp_link_down()
666 unsigned int lane_mask = 0x0; in intel_enable_dp()
796 u8 train_set = intel_dp->train_set[0]; in vlv_set_signal_levels()
[all …]
/openbmc/linux/drivers/net/ethernet/intel/e1000/
H A De1000_hw.h21 e1000_undefined = 0,
40 e1000_eeprom_uninitialized = 0,
50 e1000_media_type_copper = 0,
57 e1000_10_half = 0,
65 E1000_FC_NONE = 0,
69 E1000_FC_DEFAULT = 0xFF
79 e1000_bus_type_unknown = 0,
87 e1000_bus_speed_unknown = 0,
98 e1000_bus_width_unknown = 0,
106 e1000_cable_length_50 = 0,
[all …]
/openbmc/linux/drivers/net/ethernet/nvidia/
H A Dforcedeth.c66 #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
67 #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
68 #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet form…
69 #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
70 #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
71 #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
72 #define DEV_HAS_MSI 0x0000040 /* device supports MSI */
73 #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
74 #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
75 #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
[all …]