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/openbmc/u-boot/board/aristainetos/
H A Dddr-setup2.cfg17 DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
18 DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
20 DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
21 DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
23 DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
24 DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
25 DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
27 DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
28 DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
29 DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030
[all …]
/openbmc/u-boot/board/seco/mx6quq7/
H A Dmx6quq7-2g.cfg27 DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
28 DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
31 DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
32 DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028
33 DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028
34 DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028
35 DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028
36 DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000028
37 DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000028
38 DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000028
[all …]
/openbmc/u-boot/board/bachmann/ot1200/
H A Dot1200_spl.c12 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */
13 .dram_sdclk_0 = 0x00000028,
14 .dram_sdclk_1 = 0x00000028,
15 .dram_cas = 0x00000028,
16 .dram_ras = 0x00000028,
17 .dram_reset = 0x00000028,
18 /* SDCKE[0:1]: 100k pull-up */
19 .dram_sdcke0 = 0x00003000,
20 .dram_sdcke1 = 0x00003000,
22 .dram_sdba2 = 0x00000000,
[all …]
/openbmc/u-boot/board/samtec/vining_2000/
H A Dimximage.cfg33 DATA 4 0x020c4068 0xffffffff
34 DATA 4 0x020c406c 0xffffffff
35 DATA 4 0x020c4070 0xffffffff
36 DATA 4 0x020c4074 0xffffffff
37 DATA 4 0x020c4078 0xffffffff
38 DATA 4 0x020c407c 0xffffffff
39 DATA 4 0x020c4080 0xffffffff
40 DATA 4 0x020c4084 0xffffffff
43 DATA 4 0x020e0618 0x000c0000
44 DATA 4 0x020e05fc 0x00000000
[all …]
/openbmc/u-boot/board/freescale/mx6sxsabresd/
H A Dimximage.cfg33 DATA 4 0x020c4068 0xffffffff
34 DATA 4 0x020c406c 0xffffffff
35 DATA 4 0x020c4070 0xffffffff
36 DATA 4 0x020c4074 0xffffffff
37 DATA 4 0x020c4078 0xffffffff
38 DATA 4 0x020c407c 0xffffffff
39 DATA 4 0x020c4080 0xffffffff
40 DATA 4 0x020c4084 0xffffffff
43 DATA 4 0x020e0618 0x000c0000
44 DATA 4 0x020e05fc 0x00000000
[all …]
H A Dmx6sxsabresd.c59 return 0; in dram_init()
114 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); in setup_fec()
116 ret = enable_fec_anatop_clock(0, ENET_125MHZ); in setup_fec()
125 gpio_direction_output(IMX_GPIO_NR(2, 6) , 0); in setup_fec()
129 gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); in setup_fec()
137 return 0; in setup_fec()
159 if (ret < 0) in power_init_board()
168 return 0; in power_init_board()
175 * Phy control debug reg 0 in board_phy_config()
177 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); in board_phy_config()
[all …]
/openbmc/u-boot/board/freescale/mx6sabreauto/
H A Dmx6sabreauto.c69 return 0; in dram_init()
213 writel(0x00020181, &weim_regs->cs0gcr1); in eimnor_cs_setup()
214 writel(0x00000001, &weim_regs->cs0gcr2); in eimnor_cs_setup()
215 writel(0x0a020000, &weim_regs->cs0rcr1); in eimnor_cs_setup()
216 writel(0x0000c000, &weim_regs->cs0rcr2); in eimnor_cs_setup()
217 writel(0x0804a240, &weim_regs->cs0wcr1); in eimnor_cs_setup()
218 writel(0x00000120, &weim_regs->wcr); in eimnor_cs_setup()
231 ccgr6 &= ~(0x3 << 10); in eim_clk_setup()
246 ccgr6 |= (0x3 << 10); in eim_clk_setup()
254 gpio_direction_output(IMX_GPIO_NR(5, 4), 0); in setup_iomux_eimnor()
[all …]
/openbmc/u-boot/board/solidrun/mx6cuboxi/
H A Dmx6cuboxi.c58 #define USB_H1_VBUS IMX_GPIO_NR(1, 0)
61 CUBOXI = 0x00,
62 HUMMINGBOARD = 0x01,
63 HUMMINGBOARD2 = 0x02,
64 UNKNOWN = 0x03,
67 #define MEM_STRIDE 0x4000000
74 int i = 0; in get_ram_size_stride_test()
77 for (cnt = 0; cnt < maxsize; cnt += MEM_STRIDE) { in get_ram_size_stride_test()
85 * (volatile u32 *)base = 0x12345678; in get_ram_size_stride_test()
95 for (cnt = (maxsize - MEM_STRIDE); i > 0; cnt -= MEM_STRIDE) { in get_ram_size_stride_test()
[all …]
/openbmc/u-boot/board/phytec/pfla02/
H A Dpfla02.c61 #define IMX6Q_DRIVE_STRENGTH 0x30
66 return 0; in dram_init()
193 int ret = 0; in board_mmc_getcd()
214 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { in board_mmc_init()
216 case 0: in board_mmc_init()
218 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in board_mmc_init()
237 return 0; in board_mmc_init()
250 gpio_direction_output(ENET_PHY_RESET_GPIO, 0); in setup_iomux_enet()
287 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | in setup_gpmi_nand()
315 for (i = 0, rev = 0; i < 4; i++) in get_board_rev()
[all …]
/openbmc/u-boot/board/udoo/neo/
H A Dneo.c78 return 0; in dram_init()
88 .gp = IMX_GPIO_NR(1, 0),
116 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); in power_init_board()
120 reg |= 0x1; in power_init_board()
125 ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc); in power_init_board()
129 ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc); in power_init_board()
133 ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc); in power_init_board()
137 ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc); in power_init_board()
143 reg &= ~0x3f; in power_init_board()
151 reg &= ~0x3f; in power_init_board()
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dregsnv04.h5 #define NV04_PFB_BOOT_0 0x00100000
6 # define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003
7 # define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000
8 # define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001
9 # define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002
10 # define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003
11 # define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x00000004
12 # define NV04_PFB_BOOT_0_RAM_TYPE 0x00000028
13 # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000
14 # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dcs35l45-tables.c15 { 0x00000040, 0x00000055 },
16 { 0x00000040, 0x000000AA },
17 { 0x00000044, 0x00000055 },
18 { 0x00000044, 0x000000AA },
19 { 0x00006480, 0x0830500A },
20 { 0x00007C60, 0x1000850B },
21 { CS35L45_BOOST_OV_CFG, 0x007000D0 },
22 { CS35L45_LDPM_CONFIG, 0x0001B636 },
23 { 0x00002C08, 0x00000009 },
24 { 0x00006850, 0x0A30FFC4 },
[all …]
/openbmc/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi.xml.h57 HDCP_KEYS_STATE_NO_KEYS = 0,
68 DDC_WRITE = 0,
73 ACR_NONE = 0,
79 #define REG_HDMI_CTRL 0x00000000
80 #define HDMI_CTRL_ENABLE 0x00000001
81 #define HDMI_CTRL_HDMI 0x00000002
82 #define HDMI_CTRL_ENCRYPTED 0x00000004
84 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
85 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
87 #define REG_HDMI_ACR_PKT_CTRL 0x00000024
[all …]
/openbmc/linux/include/linux/amba/
H A Dclcd-regs.h17 #define CLCD_TIM0 0x00000000
18 #define CLCD_TIM1 0x00000004
19 #define CLCD_TIM2 0x00000008
20 #define CLCD_TIM3 0x0000000c
21 #define CLCD_UBAS 0x00000010
22 #define CLCD_LBAS 0x00000014
24 #define CLCD_PL110_IENB 0x00000018
25 #define CLCD_PL110_CNTL 0x0000001c
26 #define CLCD_PL110_STAT 0x00000020
27 #define CLCD_PL110_INTR 0x00000024
[all …]
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dhsw_clear_kernel.c9 0x00000001, 0x26020128, 0x00000024, 0x00000000,
10 0x00000040, 0x20280c21, 0x00000028, 0x00000001,
11 0x01000010, 0x20000c20, 0x0000002c, 0x00000000,
12 0x00010220, 0x34001c00, 0x00001400, 0x00000160,
13 0x00600001, 0x20600061, 0x00000000, 0x00000000,
14 0x00000008, 0x20601c85, 0x00000e00, 0x0000000c,
15 0x00000005, 0x20601ca5, 0x00000060, 0x00000001,
16 0x00000008, 0x20641c85, 0x00000e00, 0x0000000d,
17 0x00000005, 0x20641ca5, 0x00000064, 0x00000003,
18 0x00000041, 0x207424a5, 0x00000064, 0x00000034,
[all …]
H A Divb_clear_kernel.c9 0x00000001, 0x26020128, 0x00000024, 0x00000000,
10 0x00000040, 0x20280c21, 0x00000028, 0x00000001,
11 0x01000010, 0x20000c20, 0x0000002c, 0x00000000,
12 0x00010220, 0x34001c00, 0x00001400, 0x0000002c,
13 0x00600001, 0x20600061, 0x00000000, 0x00000000,
14 0x00000008, 0x20601c85, 0x00000e00, 0x0000000c,
15 0x00000005, 0x20601ca5, 0x00000060, 0x00000001,
16 0x00000008, 0x20641c85, 0x00000e00, 0x0000000d,
17 0x00000005, 0x20641ca5, 0x00000064, 0x00000003,
18 0x00000041, 0x207424a5, 0x00000064, 0x00000034,
[all …]
/openbmc/linux/drivers/media/platform/rockchip/rkisp1/
H A Drkisp1-regs.h12 #define RKISP1_CIF_ISP_CTRL_ISP_ENABLE BIT(0)
13 #define RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
32 #define RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
35 #define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
40 #define RKISP1_CIF_ISP_ACQ_PROP_YCBYCR (0 << 7)
44 #define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL (0 << 9)
47 #define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B (0 << 12)
54 #define RKISP1_CIF_VI_DPCL_DMA_JPEG (0 << 0)
55 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI (1 << 0)
56 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_JPEG (2 << 0)
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
H A Dphytbl_lcn.c10 0x00000000,
11 0x00000000,
12 0x00000000,
13 0x00000000,
14 0x00000000,
15 0x00000000,
16 0x00000000,
17 0x00000000,
18 0x00000004,
19 0x00000000,
[all …]
/openbmc/linux/drivers/gpu/drm/msm/dp/
H A Ddp_reg.h10 #define REG_DP_HW_VERSION (0x00000000)
12 #define REG_DP_SW_RESET (0x00000010)
13 #define DP_SW_RESET (0x00000001)
15 #define REG_DP_PHY_CTRL (0x00000014)
16 #define DP_PHY_CTRL_SW_RESET_PLL (0x00000001)
17 #define DP_PHY_CTRL_SW_RESET (0x00000004)
19 #define REG_DP_CLK_CTRL (0x00000018)
20 #define REG_DP_CLK_ACTIVE (0x0000001C)
21 #define REG_DP_INTR_STATUS (0x00000020)
22 #define REG_DP_INTR_STATUS2 (0x00000024)
[all …]
/openbmc/linux/drivers/gpu/drm/pl111/
H A Dpl111_drm.h29 #define CLCD_TIM0 0x00000000
30 #define CLCD_TIM1 0x00000004
31 #define CLCD_TIM2 0x00000008
32 #define CLCD_TIM3 0x0000000c
33 #define CLCD_UBAS 0x00000010
34 #define CLCD_LBAS 0x00000014
36 #define CLCD_PL110_IENB 0x00000018
37 #define CLCD_PL110_CNTL 0x0000001c
38 #define CLCD_PL110_STAT 0x00000020
39 #define CLCD_PL110_INTR 0x00000024
[all …]
/openbmc/linux/drivers/gpu/drm/msm/dsi/
H A Ddsi_phy_14nm.xml.h56 #define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000
58 #define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004
60 #define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008
62 #define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c
64 #define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010
65 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0
71 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0
78 #define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014
79 #define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001
81 #define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018
[all …]
H A Ddsi_phy_10nm.xml.h56 #define REG_DSI_10nm_PHY_CMN_REVISION_ID0 0x00000000
58 #define REG_DSI_10nm_PHY_CMN_REVISION_ID1 0x00000004
60 #define REG_DSI_10nm_PHY_CMN_REVISION_ID2 0x00000008
62 #define REG_DSI_10nm_PHY_CMN_REVISION_ID3 0x0000000c
64 #define REG_DSI_10nm_PHY_CMN_CLK_CFG0 0x00000010
66 #define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014
68 #define REG_DSI_10nm_PHY_CMN_GLBL_CTRL 0x00000018
70 #define REG_DSI_10nm_PHY_CMN_RBUF_CTRL 0x0000001c
72 #define REG_DSI_10nm_PHY_CMN_VREG_CTRL 0x00000020
74 #define REG_DSI_10nm_PHY_CMN_CTRL_0 0x00000024
[all …]
H A Ddsi_phy_28nm_8960.xml.h56 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN()
58 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_0()
60 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_1()
62 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_2()
64 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x… in REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH()
66 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*… in REG_DSI_28nm_8960_PHY_LN_TEST_STR_0()
68 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*… in REG_DSI_28nm_8960_PHY_LN_TEST_STR_1()
70 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100
72 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104
74 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar956x_initvals.h41 {0x00009800, 0xafe68e30},
42 {0x00009804, 0xfd14e000},
43 {0x00009808, 0x9c0a9f6b},
44 {0x0000980c, 0x04900000},
45 {0x00009814, 0x0280c00a},
46 {0x00009818, 0x00000000},
47 {0x0000981c, 0x00020028},
48 {0x00009834, 0x6400a190},
49 {0x00009838, 0x0108ecff},
50 {0x0000983c, 0x14000600},
[all …]
/openbmc/u-boot/include/
H A Dmb862xx.h14 #define PCI_VENDOR_ID_FUJITSU 0x10CF
15 #define PCI_DEVICE_ID_CORAL_P 0x2019
16 #define PCI_DEVICE_ID_CORAL_PA 0x201E
18 #define MB862XX_TYPE_LIME 0x1
20 #define GC_HOST_BASE 0x01fc0000
21 #define GC_DISP_BASE 0x01fd0000
22 #define GC_DRAW_BASE 0x01ff0000
25 #define GC_SRST 0x0000002c
26 #define GC_CCF 0x00000038
27 #define GC_CID 0x000000f0
[all …]

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