1*83d290c5STom Rini/* SPDX-License-Identifier: GPL-2.0+ */ 214a16131SFabio Estevam/* 314a16131SFabio Estevam * Copyright (C) 2014 Freescale Semiconductor, Inc. 414a16131SFabio Estevam */ 514a16131SFabio Estevam 614a16131SFabio Estevam#define __ASSEMBLY__ 714a16131SFabio Estevam#include <config.h> 814a16131SFabio Estevam 914a16131SFabio Estevam/* image version */ 1014a16131SFabio Estevam 1114a16131SFabio EstevamIMAGE_VERSION 2 1214a16131SFabio Estevam 1314a16131SFabio Estevam/* 1414a16131SFabio Estevam * Boot Device : one of 1514a16131SFabio Estevam * spi/sd/nand/onenand, qspi/nor 1614a16131SFabio Estevam */ 1714a16131SFabio Estevam 1814a16131SFabio EstevamBOOT_FROM sd 1914a16131SFabio Estevam 2014a16131SFabio Estevam/* 2114a16131SFabio Estevam * Device Configuration Data (DCD) 2214a16131SFabio Estevam * 2314a16131SFabio Estevam * Each entry must have the format: 2414a16131SFabio Estevam * Addr-type Address Value 2514a16131SFabio Estevam * 2614a16131SFabio Estevam * where: 2714a16131SFabio Estevam * Addr-type register length (1,2 or 4 bytes) 2814a16131SFabio Estevam * Address absolute address of the register 2914a16131SFabio Estevam * value value to be stored in the register 3014a16131SFabio Estevam */ 3114a16131SFabio Estevam 32eb5c1807SFabio Estevam/* Enable all clocks */ 3314a16131SFabio EstevamDATA 4 0x020c4068 0xffffffff 3414a16131SFabio EstevamDATA 4 0x020c406c 0xffffffff 3514a16131SFabio EstevamDATA 4 0x020c4070 0xffffffff 3614a16131SFabio EstevamDATA 4 0x020c4074 0xffffffff 3714a16131SFabio EstevamDATA 4 0x020c4078 0xffffffff 3814a16131SFabio EstevamDATA 4 0x020c407c 0xffffffff 3914a16131SFabio EstevamDATA 4 0x020c4080 0xffffffff 4014a16131SFabio EstevamDATA 4 0x020c4084 0xffffffff 4114a16131SFabio Estevam 42eb5c1807SFabio Estevam/* IOMUX - DDR IO Type */ 4314a16131SFabio EstevamDATA 4 0x020e0618 0x000c0000 4414a16131SFabio EstevamDATA 4 0x020e05fc 0x00000000 45eb5c1807SFabio Estevam 46eb5c1807SFabio Estevam/* Clock */ 4714a16131SFabio EstevamDATA 4 0x020e032c 0x00000030 4814a16131SFabio Estevam 49eb5c1807SFabio Estevam/* Address */ 50eb5c1807SFabio EstevamDATA 4 0x020e0300 0x00000020 51eb5c1807SFabio EstevamDATA 4 0x020e02fc 0x00000020 52eb5c1807SFabio EstevamDATA 4 0x020e05f4 0x00000020 53eb5c1807SFabio Estevam 54eb5c1807SFabio Estevam/* Control */ 55eb5c1807SFabio EstevamDATA 4 0x020e0340 0x00000020 5614a16131SFabio Estevam 5714a16131SFabio EstevamDATA 4 0x020e0320 0x00000000 58eb5c1807SFabio EstevamDATA 4 0x020e0310 0x00000020 59eb5c1807SFabio EstevamDATA 4 0x020e0314 0x00000020 60eb5c1807SFabio EstevamDATA 4 0x020e0614 0x00000020 6114a16131SFabio Estevam 62eb5c1807SFabio Estevam/* Data Strobe */ 6314a16131SFabio EstevamDATA 4 0x020e05f8 0x00020000 64eb5c1807SFabio EstevamDATA 4 0x020e0330 0x00000028 65eb5c1807SFabio EstevamDATA 4 0x020e0334 0x00000028 66eb5c1807SFabio EstevamDATA 4 0x020e0338 0x00000028 67eb5c1807SFabio EstevamDATA 4 0x020e033c 0x00000028 68eb5c1807SFabio Estevam 69eb5c1807SFabio Estevam/* Data */ 7014a16131SFabio EstevamDATA 4 0x020e0608 0x00020000 71eb5c1807SFabio EstevamDATA 4 0x020e060c 0x00000028 72eb5c1807SFabio EstevamDATA 4 0x020e0610 0x00000028 73eb5c1807SFabio EstevamDATA 4 0x020e061c 0x00000028 74eb5c1807SFabio EstevamDATA 4 0x020e0620 0x00000028 75eb5c1807SFabio EstevamDATA 4 0x020e02ec 0x00000028 76eb5c1807SFabio EstevamDATA 4 0x020e02f0 0x00000028 77eb5c1807SFabio EstevamDATA 4 0x020e02f4 0x00000028 78eb5c1807SFabio EstevamDATA 4 0x020e02f8 0x00000028 79eb5c1807SFabio Estevam 80eb5c1807SFabio Estevam/* Calibrations - ZQ */ 8114a16131SFabio EstevamDATA 4 0x021b0800 0xa1390003 82eb5c1807SFabio Estevam 83eb5c1807SFabio Estevam/* Write leveling */ 84eb5c1807SFabio EstevamDATA 4 0x021b080c 0x00290025 85eb5c1807SFabio EstevamDATA 4 0x021b0810 0x00220022 86eb5c1807SFabio Estevam 87eb5c1807SFabio Estevam/* DQS Read Gate */ 88eb5c1807SFabio EstevamDATA 4 0x021b083c 0x41480144 89eb5c1807SFabio EstevamDATA 4 0x021b0840 0x01340130 90eb5c1807SFabio Estevam 91eb5c1807SFabio Estevam/* Read/Write Delay */ 92eb5c1807SFabio EstevamDATA 4 0x021b0848 0x3C3E4244 93eb5c1807SFabio EstevamDATA 4 0x021b0850 0x34363638 94eb5c1807SFabio Estevam 95eb5c1807SFabio Estevam/* Read data bit delay */ 9614a16131SFabio EstevamDATA 4 0x021b081c 0x33333333 9714a16131SFabio EstevamDATA 4 0x021b0820 0x33333333 9814a16131SFabio EstevamDATA 4 0x021b0824 0x33333333 9914a16131SFabio EstevamDATA 4 0x021b0828 0x33333333 100eb5c1807SFabio Estevam 101eb5c1807SFabio Estevam/* Complete calibration by forced measurement */ 10214a16131SFabio EstevamDATA 4 0x021b08b8 0x00000800 103eb5c1807SFabio Estevam 104eb5c1807SFabio Estevam/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */ 10514a16131SFabio EstevamDATA 4 0x021b0004 0x0002002d 10614a16131SFabio EstevamDATA 4 0x021b0008 0x00333030 10714a16131SFabio EstevamDATA 4 0x021b000c 0x676b52f3 10814a16131SFabio EstevamDATA 4 0x021b0010 0xb66d8b63 10914a16131SFabio EstevamDATA 4 0x021b0014 0x01ff00db 11014a16131SFabio EstevamDATA 4 0x021b0018 0x00011740 11114a16131SFabio EstevamDATA 4 0x021b001c 0x00008000 11214a16131SFabio EstevamDATA 4 0x021b002c 0x000026d2 11314a16131SFabio EstevamDATA 4 0x021b0030 0x006b1023 11414a16131SFabio EstevamDATA 4 0x021b0040 0x0000005f 11514a16131SFabio EstevamDATA 4 0x021b0000 0x84190000 116eb5c1807SFabio Estevam 117eb5c1807SFabio Estevam/* Initialize MT41K256M16HA-125 - MR2 */ 11814a16131SFabio EstevamDATA 4 0x021b001c 0x04008032 119eb5c1807SFabio Estevam/* MR3 */ 12014a16131SFabio EstevamDATA 4 0x021b001c 0x00008033 121eb5c1807SFabio Estevam/* MR1 */ 122eb5c1807SFabio EstevamDATA 4 0x021b001c 0x00048031 123eb5c1807SFabio Estevam/* MR0 */ 12414a16131SFabio EstevamDATA 4 0x021b001c 0x05208030 125eb5c1807SFabio Estevam/* DDR device ZQ calibration */ 12614a16131SFabio EstevamDATA 4 0x021b001c 0x04008040 127eb5c1807SFabio Estevam 128eb5c1807SFabio Estevam/* Final DDR setup, before operation start */ 12914a16131SFabio EstevamDATA 4 0x021b0020 0x00000800 13014a16131SFabio EstevamDATA 4 0x021b0818 0x00011117 13114a16131SFabio EstevamDATA 4 0x021b001c 0x00000000 132