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/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dnand_ids.c23 * If page size and eraseblock size are 0, the sizes are taken from the
28 LEGACY_ID_NAND("NAND 1MiB 5V 8-bit", 0x6e, 1, SZ_4K, SP_OPTIONS),
29 LEGACY_ID_NAND("NAND 2MiB 5V 8-bit", 0x64, 2, SZ_4K, SP_OPTIONS),
30 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS),
31 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS),
32 LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS),
33 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS),
35 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS),
42 {"TC58NVG0S3E 1G 3.3V 8-bit",
43 { .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
[all …]
/openbmc/linux/drivers/mtd/nand/raw/
H A Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #define LP_OPTIONS 0
20 * If page size and eraseblock size are 0, the sizes are taken from the
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
30 { .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
33 { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
[all …]
/openbmc/linux/Documentation/driver-api/media/drivers/ccs/
H A Dccs-regs.asc1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
12 # 8, 16, 32 register bits (default is 8)
19 module_model_id 0x0000 16
20 module_revision_number_major 0x0002 8
[all …]
/openbmc/linux/arch/powerpc/boot/
H A Dwii-head.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * arch/powerpc/boot/wii-head.S
6 * Copyright (C) 2008-2009 The GameCube Linux Team
14 * - if the data and instruction caches are enabled or not
15 * - if the MMU is enabled or not
16 * - if the high BATs are enabled or not
29 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
32 mflr 8
33 clrlwi 8, 8, 3 /* convert to a real address */
34 addi 8, 8, _mmu_off - 1b
[all …]
H A Dgamecube-head.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * arch/powerpc/boot/gamecube-head.S
6 * Copyright (C) 2004-2009 The GameCube Linux Team
14 * - if the data and instruction caches are enabled or not
15 * - if the MMU is enabled or not
28 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
31 mflr 8
32 clrlwi 8, 8, 3 /* convert to a real address */
33 addi 8, 8, _mmu_off - 1b
34 mtsrr0 8
[all …]
/openbmc/u-boot/drivers/gpio/
H A Dda8xx_gpio.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <dt-bindings/gpio/gpio.h>
28 #define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
32 { pinmux(13), 8, 6 }, /* GP0[0] */
33 { pinmux(13), 8, 7 },
34 { pinmux(14), 8, 0 },
35 { pinmux(14), 8, 1 },
36 { pinmux(14), 8, 2 },
37 { pinmux(14), 8, 3 },
38 { pinmux(14), 8, 4 },
[all …]
/openbmc/qemu/include/libdecnumber/
H A DdecDPD.h29 02110-1301, USA. */
31 /* ------------------------------------------------------------------------ */
33 /* [Automatically generated -- do not edit. 2007.05.05] */
34 /* ------------------------------------------------------------------------ */
35 /* ------------------------------------------------------------------------ */
41 /* uint16_t BCD2DPD[2458]; -- BCD -> DPD (0x999 => 2457) */
42 /* uint16_t BIN2DPD[1000]; -- Bin -> DPD (999 => 2457) */
43 /* uint8_t BIN2CHAR[4001]; -- Bin -> CHAR (999 => '\3' '9' '9' '9') */
44 /* uint8_t BIN2BCD8[4000]; -- Bin -> bytes (999 => 9 9 9 3) */
45 /* uint16_t DPD2BCD[1024]; -- DPD -> BCD (0x3FF => 0x999) */
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/
H A Dmdp_format.c1 // SPDX-License-Identifier: GPL-2.0-only
18 0x0200, 0x0000, 0x0000,
19 0x0000, 0x0200, 0x0000,
20 0x0000, 0x0000, 0x0200
22 .pre_bias = { 0x0, 0x0, 0x0 },
23 .post_bias = { 0x0, 0x0, 0x0 },
24 .pre_clamp = { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff },
25 .post_clamp = { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff },
30 0x0254, 0x0000, 0x0331,
31 0x0254, 0xff37, 0xfe60,
[all …]
/openbmc/u-boot/include/fsl-mc/
H A Dfsl_dprc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright 2013-2016 Freescale Semiconductor, Inc.
16 #define DPRC_CMDID_CLOSE 0x8001
17 #define DPRC_CMDID_OPEN 0x8051
18 #define DPRC_CMDID_CREATE 0x9051
20 #define DPRC_CMDID_GET_ATTR 0x0041
21 #define DPRC_CMDID_RESET_CONT 0x0051
22 #define DPRC_CMDID_GET_API_VERSION 0xa051
24 #define DPRC_CMDID_CREATE_CONT 0x1511
25 #define DPRC_CMDID_DESTROY_CONT 0x1521
[all …]
/openbmc/linux/arch/powerpc/perf/
H A Dhv-gpci-requests.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 #include "req-gen/_begin.h"
22 * - starting_index_kind is one of the following, depending on the event:
24 * hw_chip_id: hardware chip id or -1 for current hw chip
28 * 0xffffffffffffffff: or -1, which means it is irrelavant for the event
43 * - expose secondary index (if any counter ever uses it, only 0xA0
45 * - embed versioning info
46 * - include counter descriptions
49 #define REQUEST_NUM 0x10
52 REQUEST(__count(0, 8, processor_time_in_timebase_cycles)
[all …]
/openbmc/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2014 Tensilica Inc.
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
44 #define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
48 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
50 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
53 #define XCHAL_CP0_SA_SIZE 0
[all …]
/openbmc/linux/fs/nls/
H A Dnls_ucs2_utils.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 000-00f */
26 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 010-01f */
27 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 020-02f */
28 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 030-03f */
29 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 040-04f */
30 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 050-05f */
31 0, -32, -32, -32, -32, -32, -32, -32, -32, -32, -32,
32 -32, -32, -32, -32, -32, /* 060-06f */
33 -32, -32, -32, -32, -32, -32, -32, -32, -32, -32,
[all …]
/openbmc/u-boot/arch/nios2/lib/
H A Dlibgcc.c1 // SPDX-License-Identifier: GPL-2.0+
32 #define BITS_PER_UNIT 8
39 0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
43 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
44 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
45 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
46 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8
53 if (b == 0) in __ashldi3()
57 const word_type bm = (sizeof (Wtype) * BITS_PER_UNIT) - b; in __ashldi3()
60 if (bm <= 0) in __ashldi3()
[all …]
/openbmc/linux/drivers/mfd/
H A Dmt6370.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #define MT6370_REG_DEV_INFO 0x100
20 #define MT6370_REG_CHG_IRQ1 0x1C0
21 #define MT6370_REG_CHG_MASK1 0x1E0
22 #define MT6370_REG_MAXADDR 0x1FF
27 #define MT6370_USBC_I2CADDR 0x4E
30 #define MT6370_VENID_RT5081 0x8
31 #define MT6370_VENID_RT5081A 0xA
32 #define MT6370_VENID_MT6370 0xE
33 #define MT6370_VENID_MT6371 0xF
[all …]
H A Dmt6360-core.c1 // SPDX-License-Identifier: GPL-2.0
19 MT6360_SLAVE_TCPC = 0,
35 #define MT6360_TCPC_SLAVEID 0x4E
36 #define MT6360_PMIC_SLAVEID 0x1A
37 #define MT6360_LDO_SLAVEID 0x64
38 #define MT6360_PMU_SLAVEID 0x34
40 #define MT6360_REG_TCPCSTART 0x00
41 #define MT6360_REG_TCPCEND 0xFF
42 #define MT6360_REG_PMICSTART 0x100
43 #define MT6360_REG_PMICEND 0x13B
[all …]
/openbmc/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos-arm.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include <linux/soc/samsung/exynos-regs-pmu.h>
22 #include "pinctrl-samsung.h"
23 #include "pinctrl-exynos.h"
27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
45 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; in s5pv210_retention_disable()
62 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); in s5pv210_retention_init()
64 return ERR_PTR(-ENOMEM); in s5pv210_retention_init()
[all …]
/openbmc/linux/Documentation/gpu/
H A Dafbc.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 It provides fine-grained random access and minimizes the amount of
21 AFBC streams can contain several components - where a component
31 * Component 0: R
36 fourcc:modifier pair. In general, component '0' is considered to
37 reside in the least-significant bits of the corresponding linear
42 * Component 0: R(8)
43 * Component 1: G(8)
44 * Component 2: B(8)
45 * Component 3: A(8)
[all …]
/openbmc/linux/drivers/media/test-drivers/vicodec/
H A Dcodec-fwht.c1 // SPDX-License-Identifier: LGPL-2.1+
6 * 8x8 Fast Walsh Hadamard Transform in sequency order based on the paper:
8 * A Recursive Algorithm for Sequency-Ordered Fast Walsh Transforms,
15 #include "codec-fwht.h"
20 * Note: bit 0 of the header must always be 0. Otherwise it cannot
21 * be guaranteed that the magic 8 byte sequence (see below) can
25 #define DUPS_MASK 0x1ffe
27 #define PBLOCK 0
33 0,
34 1, 8,
[all …]
/openbmc/openbmc/meta-hpe/meta-dl360-g11/recipes-hpe/power-sequencing/files/
H A Dgpios-manager.sh5 …busctl set-property xyz.openbmc_project.Chassis.Gpios /xyz/openbmc_project/chassis/gpios xyz.openb…
6 devmem 0x80fc0230 8 0x1
8 devmem 0x80fc0230 8 0x1
11 devmem 0xd1000087 8 1
12 i2ctransfer -y 3 w4@0x40 0x34 0xbf 0x00 0xe8
13 devmem 0xd1000087 8 2
14 i2ctransfer -y 3 w4@0x40 0x34 0xbf 0x00 0xe8
15 devmem 0xd1000087 8 3
16 i2ctransfer -y 3 w4@0x40 0x34 0xbf 0x00 0xe8
17 devmem 0xd1000087 8 4
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap3-echo.dts1 // SPDX-License-Identifier: GPL-2.0-only
5 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
14 compatible = "amazon,omap3-echo", "ti,omap3630", "ti,omap3";
17 cpu@0 {
18 cpu0-supply = <&vdd1_reg>;
24 reg = <0x80000000 0xc600000>; /* 198 MB */
28 compatible = "regulator-fixed";
29 regulator-name = "vcc5v";
[all …]
/openbmc/linux/drivers/gpu/drm/display/
H A Ddrm_dsc_helper.c1 // SPDX-License-Identifier: MIT
34 * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
46 memset(pps_header, 0, sizeof(*pps_header)); in drm_dsc_dp_pps_header_init()
48 pps_header->HB1 = DP_SDP_PPS; in drm_dsc_dp_pps_header_init()
49 pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1; in drm_dsc_dp_pps_header_init()
54 * drm_dsc_dp_rc_buffer_size - get rc buffer size in bytes
56 * @rc_buffer_size: number of blocks - 1, according to DPCD offset 63h
59 * buffer size in bytes, or 0 on invalid input
75 return 0; in drm_dsc_dp_rc_buffer_size()
81 * drm_dsc_pps_payload_pack() - Populates the DSC PPS
[all …]
/openbmc/qemu/hw/net/can/
H A Dxlnx-versal-canfd.c5 * https://docs.xilinx.com/v/u/2.0-English/pg223-canfd
9 * Written-by: Vikram Garhwal <vikram.garhwal@amd.com>
42 #include "hw/qdev-properties.h"
45 #include "hw/net/xlnx-versal-canfd.h"
48 REG32(SOFTWARE_RESET_REGISTER, 0x0)
50 FIELD(SOFTWARE_RESET_REGISTER, SRST, 0, 1)
51 REG32(MODE_SELECT_REGISTER, 0x4)
52 FIELD(MODE_SELECT_REGISTER, ITO, 8, 8)
60 FIELD(MODE_SELECT_REGISTER, SLEEP, 0, 1)
61 REG32(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, 0x8)
[all …]
/openbmc/linux/arch/arm/crypto/
H A Daes-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * aes-ce-core.S - AES in CBC/CTR/XTS mode using ARMv8 Crypto Extensions
12 .arch armv8-a
13 .fpu crypto-neon-fp-armv8
17 aese.8 \state, \key
18 aesmc.8 \state, \state
22 aesd.8 \state, \key
23 aesimc.8 \state, \state
38 aese.8 q0, \key2
44 aesd.8 q0, \key2
[all …]
/openbmc/linux/arch/arc/include/asm/
H A Darcregs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
10 #define ARC_REG_AUX_DCCM 0x18 /* DCCM Base Addr ARCv2 */
11 #define ARC_REG_ERP_CTRL 0x3F /* ARCv2 Error protection control */
12 #define ARC_REG_DCCM_BASE_BUILD 0x61 /* DCCM Base Addr ARCompact */
13 #define ARC_REG_CRC_BCR 0x62
14 #define ARC_REG_VECBASE_BCR 0x68
15 #define ARC_REG_PERIBASE_BCR 0x69
16 #define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */
17 #define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */
[all …]
/openbmc/linux/arch/arm/mach-davinci/
H A Dda830.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
14 #include <linux/irqchip/irq-davinci-cp-intc.h>
16 #include <clocksource/timer-davinci.h>
26 /* Offsets of the 8 compare registers on the da830 */
27 #define DA830_CMP12_0 0x60
28 #define DA830_CMP12_1 0x64
29 #define DA830_CMP12_2 0x68
30 #define DA830_CMP12_3 0x6c
31 #define DA830_CMP12_4 0x70
[all …]

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