/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | renesas,cpg-mssr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Geert Uytterhoeven <geert+renesas@glider.be> 13 On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator) 14 and MSSR (Module Standby and Software Reset) blocks are intimately connected, 18 - The CPG block generates various core clocks, 19 - The MSSR block provides two functions: 27 - renesas,r7s9210-cpg-mssr # RZ/A2 [all …]
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/openbmc/linux/drivers/clk/renesas/ |
H A D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0 3 obj-$(CONFIG_CLK_EMEV2) += clk-emev2.o 4 obj-$(CONFIG_CLK_RZA1) += clk-rz.o 5 obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o 6 obj-$(CONFIG_CLK_R8A73A4) += clk-r8a73a4.o 7 obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o 8 obj-$(CONFIG_CLK_R8A7742) += r8a7742-cpg-mssr.o 9 obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o 10 obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o 11 obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o [all …]
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H A D | renesas-cpg-mssr.c | 1 // SPDX-License-Identifier: GPL-2.0 7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c 14 #include <linux/clk-provider.h> 28 #include <linux/reset-controller.h> 31 #include <dt-bindings/clock/renesas-cpg-mssr.h> 33 #include "renesas-cpg-mssr.h" 34 #include "clk-div6.h" 46 * If the registers exist, these are valid for SH-Mobile, R-Mobile, 47 * R-Car Gen2, R-Car Gen3, and RZ/G1. 48 * These are NOT valid for R-Car Gen1 and RZ/A1! [all …]
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H A D | r7s9210-cpg-mssr.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Based on r8a7795-cpg-mssr.c 13 #include <linux/clk-provider.h> 15 #include <dt-bindings/clock/r7s9210-cpg-mssr.h> 16 #include "renesas-cpg-mssr.h" 169 parent = clks[core->parent]; in rza2_cpg_clk_register() 173 switch (core->id) { in rza2_cpg_clk_register() 185 return ERR_PTR(-EINVAL); in rza2_cpg_clk_register() 188 if (core->id == CLK_MAIN) in rza2_cpg_clk_register() 191 return clk_register_fixed_factor(NULL, core->name, in rza2_cpg_clk_register() [all …]
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H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0 58 bool "R-Mobile APE6 clock support" if COMPILE_TEST 63 bool "R-Mobile A1 clock support" if COMPILE_TEST 100 bool "R-Car M1A clock support" if COMPILE_TEST 104 bool "R-Car H1 clock support" if COMPILE_TEST 108 bool "R-Car H2 clock support" if COMPILE_TEST 112 bool "R-Car M2-W/N clock support" if COMPILE_TEST 116 bool "R-Car V2H clock support" if COMPILE_TEST 120 bool "R-Car E2 clock support" if COMPILE_TEST 124 bool "R-Car H3 clock support" if COMPILE_TEST [all …]
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H A D | r8a77995-cpg-mssr.c | 1 // SPDX-License-Identifier: GPL-2.0 7 * Based on r8a7795-cpg-mssr.c 16 #include <linux/soc/renesas/rcar-rst.h> 18 #include <dt-bindings/clock/r8a77995-cpg-mssr.h> 20 #include "renesas-cpg-mssr.h" 21 #include "rcar-gen3-cpg.h" 136 DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1), 137 DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1), 138 DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1), 139 DEF_MOD("sceg-pub", 229, R8A77995_CLK_CR), [all …]
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/openbmc/u-boot/drivers/clk/renesas/ |
H A D | Makefile | 1 obj-$(CONFIG_CLK_RENESAS) += renesas-cpg-mssr.o 2 obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o 3 obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o 4 obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o 5 obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o 6 obj-$(CONFIG_CLK_R8A7793) += r8a7791-cpg-mssr.o 7 obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o 8 obj-$(CONFIG_CLK_RCAR_GEN3) += clk-rcar-gen3.o 9 obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o 10 obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o [all …]
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H A D | renesas-cpg-mssr.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Renesas RCar Gen3 CPG MSSR driver 13 #include <clk-uclass.h> 19 #include <dt-bindings/clock/renesas-cpg-mssr.h> 21 #include "renesas-cpg-mssr.h" 26 * If the registers exist, these are valid for SH-Mobile, R-Mobile, 27 * R-Car Gen2, R-Car Gen3, and RZ/G1. 28 * These are NOT valid for R-Car Gen1 and RZ/A1! 56 #define RMSTPCR(i) (smstpcr[i] - 0x20) 66 return (clk->id >> 16) == CPG_MOD; in renesas_clk_is_mod() [all …]
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H A D | r8a77970-cpg-mssr.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Renesas R8A77970 CPG MSSR driver 5 * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com> 14 #include <clk-uclass.h> 17 #include <dt-bindings/clock/r8a77970-cpg-mssr.h> 19 #include "renesas-cpg-mssr.h" 20 #include "rcar-gen3-cpg.h" 110 DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ 111 DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ 114 DEF_MOD("intc-ex", 407, R8A77970_CLK_CP), [all …]
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H A D | r8a77995-cpg-mssr.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Renesas R8A77995 CPG MSSR driver 5 * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com> 14 #include <clk-uclass.h> 17 #include <dt-bindings/clock/r8a77995-cpg-mssr.h> 19 #include "renesas-cpg-mssr.h" 20 #include "rcar-gen3-cpg.h" 114 DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1), 115 DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1), 116 DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1), [all …]
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H A D | r8a7792-cpg-mssr.c | 6 * Based on clk-rcar-gen2.c 16 #include <clk-uclass.h> 19 #include <dt-bindings/clock/r8a7792-cpg-mssr.h> 21 #include "renesas-cpg-mssr.h" 22 #include "rcar-gen2-cpg.h" 86 DEF_MOD("2d-dmac", 115, R8A7792_CLK_ZS), 93 DEF_MOD("vsp1-sy", 131, R8A7792_CLK_ZS), 95 DEF_MOD("sys-dmac1", 218, R8A7792_CLK_ZS), 96 DEF_MOD("sys-dmac0", 219, R8A7792_CLK_ZS), 101 DEF_MOD("intc-sys", 408, R8A7792_CLK_ZS), [all …]
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H A D | r8a7791-cpg-mssr.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Renesas R8A7791 CPG MSSR driver 9 * Copyright (C) 2015-2017 Glider bvba 10 * Based on clk-rcar-gen2.c 15 #include <clk-uclass.h> 18 #include <dt-bindings/clock/r8a7791-cpg-mssr.h> 20 #include "renesas-cpg-mssr.h" 21 #include "rcar-gen2-cpg.h" 96 DEF_MOD("2d-dmac", 115, R8A7791_CLK_ZS), 97 DEF_MOD("fdp1-1", 118, R8A7791_CLK_ZS), [all …]
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H A D | r8a7794-cpg-mssr.c | 6 * Based on clk-rcar-gen2.c 16 #include <clk-uclass.h> 19 #include <dt-bindings/clock/r8a7794-cpg-mssr.h> 21 #include "renesas-cpg-mssr.h" 22 #include "rcar-gen2-cpg.h" 95 DEF_MOD("2d-dmac", 115, R8A7794_CLK_ZS), 96 DEF_MOD("fdp1-0", 119, R8A7794_CLK_ZS), 102 DEF_MOD("vsp1-sy", 131, R8A7794_CLK_ZS), 111 DEF_MOD("sys-dmac1", 218, R8A7794_CLK_ZS), 112 DEF_MOD("sys-dmac0", 219, R8A7794_CLK_ZS), [all …]
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H A D | renesas-cpg-mssr.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 3 * Renesas RCar Gen3 CPG MSSR driver 5 * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com> 35 * Definitions of CPG Core Clocks 38 * - Clock outputs exported to DT 39 * - External input clocks 40 * - Internal CPG clocks 88 /* Convert from sparse base-100 to packed index space */ 89 #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32)) 108 const struct mssr_mod_clk **mssr);
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H A D | r8a7796-cpg-mssr.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Renesas R8A7796 CPG MSSR driver 5 * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com> 14 #include <clk-uclass.h> 17 #include <dt-bindings/clock/r8a7796-cpg-mssr.h> 19 #include "renesas-cpg-mssr.h" 20 #include "rcar-gen3-cpg.h" 121 DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3), 122 DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3), 123 DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3), [all …]
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H A D | r8a77990-cpg-mssr.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Renesas R8A77990 CPG MSSR driver 5 * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com> 14 #include <clk-uclass.h> 17 #include <dt-bindings/clock/r8a77990-cpg-mssr.h> 19 #include "renesas-cpg-mssr.h" 20 #include "rcar-gen3-cpg.h" 129 DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1), 130 DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1), 131 DEF_MOD("sys-dmac0", 219, R8A77990_CLK_S3D1), [all …]
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/openbmc/linux/arch/arm/mach-shmobile/ |
H A D | setup-rcar-gen2.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * R-Car Generation 2 support 12 #include <linux/dma-map-ops.h> 23 #include "rcar-gen2.h" 26 { .compatible = "renesas,r8a7742-cpg-mssr", .data = "extal" }, 27 { .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" }, 28 { .compatible = "renesas,r8a7744-cpg-mssr", .data = "extal" }, 29 { .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" }, 30 { .compatible = "renesas,r8a7791-cpg-mssr", .data = "extal" }, 31 { .compatible = "renesas,r8a7793-cpg-mssr", .data = "extal" }, [all …]
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/openbmc/linux/Documentation/devicetree/bindings/media/ |
H A D | renesas,vsp1.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 13 The VSP is a video processing engine that supports up-/down-scaling, alpha 15 It can be found in the Renesas R-Car Gen2, R-Car Gen3, RZ/G1, and RZ/G2 SoCs. 20 - enum: 21 - renesas,r9a07g044-vsp2 # RZ/G2L 22 - renesas,vsp1 # R-Car Gen2 and RZ/G1 23 - renesas,vsp2 # R-Car Gen3 and RZ/G2 [all …]
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H A D | renesas,vin.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Renesas R-Car Video Input (VIN) 11 - Niklas Söderlund <niklas.soderlund@ragnatech.se> 14 The R-Car Video Input (VIN) device provides video input capabilities for the 15 Renesas R-Car family of devices. 20 on Gen3 and RZ/G2 platforms to a CSI-2 receiver. 25 - items: 26 - enum: [all …]
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/openbmc/linux/Documentation/devicetree/bindings/thermal/ |
H A D | rcar-gen3-thermal.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 4 --- 5 $id: http://devicetree.org/schemas/thermal/rcar-gen3-thermal.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Renesas R-Car Gen3 Thermal Sensor 11 On most R-Car Gen3 and later SoCs, the thermal sensor controllers (TSC) 16 - Niklas Söderlund <niklas.soderlund@ragnatech.se> 21 - renesas,r8a774a1-thermal # RZ/G2M 22 - renesas,r8a774b1-thermal # RZ/G2N 23 - renesas,r8a774e1-thermal # RZ/G2H [all …]
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/openbmc/linux/Documentation/devicetree/bindings/display/bridge/ |
H A D | renesas,lvds.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Renesas R-Car LVDS Encoder 10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 13 These DT bindings describe the LVDS encoder embedded in the Renesas R-Car 14 Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs. 19 - renesas,r8a7742-lvds # for RZ/G1H compatible LVDS encoders 20 - renesas,r8a7743-lvds # for RZ/G1M compatible LVDS encoders 21 - renesas,r8a7744-lvds # for RZ/G1N compatible LVDS encoders [all …]
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/openbmc/linux/include/dt-bindings/clock/ |
H A D | r7s9210-cpg-mssr.h | 1 /* SPDX-License-Identifier: GPL-2.0 10 #include <dt-bindings/clock/renesas-cpg-mssr.h> 12 /* R7S9210 CPG Core Clocks */
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H A D | r8a7795-cpg-mssr.h | 1 /* SPDX-License-Identifier: GPL-2.0+ 8 #include <dt-bindings/clock/renesas-cpg-mssr.h> 10 /* r8a7795 CPG Core Clocks */ 59 /* r8a7795 ES2.0 CPG Core Clocks */
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/openbmc/linux/Documentation/devicetree/bindings/phy/ |
H A D | renesas,rcar-gen3-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/renesas,rcar-gen3-pcie-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Renesas R-Car Generation 3 PCIe PHY 10 - Sergei Shtylyov <sergei.shtylyov@gmail.com> 14 const: renesas,r8a77980-pcie-phy 22 power-domains: 28 '#phy-cells': 32 - compatible [all …]
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H A D | renesas,r8a779f0-ether-serdes.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/renesas,r8a779f0-ether-serdes.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 14 const: renesas,r8a779f0-ether-serdes 25 power-domains: 28 '#phy-cells': 33 - compatible 34 - reg [all …]
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