1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2014-2018 Broadcom */
3
4 /**
5 * DOC: Interrupt management for the V3D engine
6 *
7 * When we take a bin, render, TFU done, or CSD done interrupt, we
8 * need to signal the fence for that job so that the scheduler can
9 * queue up the next one and unblock any waiters.
10 *
11 * When we take the binner out of memory interrupt, we need to
12 * allocate some new memory and pass it to the binner so that the
13 * current job can make progress.
14 */
15
16 #include <linux/platform_device.h>
17
18 #include "v3d_drv.h"
19 #include "v3d_regs.h"
20 #include "v3d_trace.h"
21
22 #define V3D_CORE_IRQS ((u32)(V3D_INT_OUTOMEM | \
23 V3D_INT_FLDONE | \
24 V3D_INT_FRDONE | \
25 V3D_INT_CSDDONE | \
26 V3D_INT_GMPV))
27
28 #define V3D_HUB_IRQS ((u32)(V3D_HUB_INT_MMU_WRV | \
29 V3D_HUB_INT_MMU_PTI | \
30 V3D_HUB_INT_MMU_CAP | \
31 V3D_HUB_INT_TFUC))
32
33 static irqreturn_t
34 v3d_hub_irq(int irq, void *arg);
35
36 static void
v3d_overflow_mem_work(struct work_struct * work)37 v3d_overflow_mem_work(struct work_struct *work)
38 {
39 struct v3d_dev *v3d =
40 container_of(work, struct v3d_dev, overflow_mem_work);
41 struct drm_device *dev = &v3d->drm;
42 struct v3d_bo *bo = v3d_bo_create(dev, NULL /* XXX: GMP */, 256 * 1024);
43 struct drm_gem_object *obj;
44 unsigned long irqflags;
45
46 if (IS_ERR(bo)) {
47 DRM_ERROR("Couldn't allocate binner overflow mem\n");
48 return;
49 }
50 obj = &bo->base.base;
51
52 /* We lost a race, and our work task came in after the bin job
53 * completed and exited. This can happen because the HW
54 * signals OOM before it's fully OOM, so the binner might just
55 * barely complete.
56 *
57 * If we lose the race and our work task comes in after a new
58 * bin job got scheduled, that's fine. We'll just give them
59 * some binner pool anyway.
60 */
61 spin_lock_irqsave(&v3d->job_lock, irqflags);
62 if (!v3d->bin_job) {
63 spin_unlock_irqrestore(&v3d->job_lock, irqflags);
64 goto out;
65 }
66
67 drm_gem_object_get(obj);
68 list_add_tail(&bo->unref_head, &v3d->bin_job->render->unref_list);
69 spin_unlock_irqrestore(&v3d->job_lock, irqflags);
70
71 V3D_CORE_WRITE(0, V3D_PTB_BPOA, bo->node.start << PAGE_SHIFT);
72 V3D_CORE_WRITE(0, V3D_PTB_BPOS, obj->size);
73
74 out:
75 drm_gem_object_put(obj);
76 }
77
78 static irqreturn_t
v3d_irq(int irq,void * arg)79 v3d_irq(int irq, void *arg)
80 {
81 struct v3d_dev *v3d = arg;
82 u32 intsts;
83 irqreturn_t status = IRQ_NONE;
84
85 intsts = V3D_CORE_READ(0, V3D_CTL_INT_STS);
86
87 /* Acknowledge the interrupts we're handling here. */
88 V3D_CORE_WRITE(0, V3D_CTL_INT_CLR, intsts);
89
90 if (intsts & V3D_INT_OUTOMEM) {
91 /* Note that the OOM status is edge signaled, so the
92 * interrupt won't happen again until the we actually
93 * add more memory. Also, as of V3D 4.1, FLDONE won't
94 * be reported until any OOM state has been cleared.
95 */
96 schedule_work(&v3d->overflow_mem_work);
97 status = IRQ_HANDLED;
98 }
99
100 if (intsts & V3D_INT_FLDONE) {
101 struct v3d_fence *fence =
102 to_v3d_fence(v3d->bin_job->base.irq_fence);
103
104 trace_v3d_bcl_irq(&v3d->drm, fence->seqno);
105 dma_fence_signal(&fence->base);
106 v3d->bin_job = NULL;
107 status = IRQ_HANDLED;
108 }
109
110 if (intsts & V3D_INT_FRDONE) {
111 struct v3d_fence *fence =
112 to_v3d_fence(v3d->render_job->base.irq_fence);
113
114 trace_v3d_rcl_irq(&v3d->drm, fence->seqno);
115 dma_fence_signal(&fence->base);
116 v3d->render_job = NULL;
117 status = IRQ_HANDLED;
118 }
119
120 if (intsts & V3D_INT_CSDDONE) {
121 struct v3d_fence *fence =
122 to_v3d_fence(v3d->csd_job->base.irq_fence);
123
124 trace_v3d_csd_irq(&v3d->drm, fence->seqno);
125 dma_fence_signal(&fence->base);
126 v3d->csd_job = NULL;
127 status = IRQ_HANDLED;
128 }
129
130 /* We shouldn't be triggering these if we have GMP in
131 * always-allowed mode.
132 */
133 if (intsts & V3D_INT_GMPV)
134 dev_err(v3d->drm.dev, "GMP violation\n");
135
136 /* V3D 4.2 wires the hub and core IRQs together, so if we &
137 * didn't see the common one then check hub for MMU IRQs.
138 */
139 if (v3d->single_irq_line && status == IRQ_NONE)
140 return v3d_hub_irq(irq, arg);
141
142 return status;
143 }
144
145 static irqreturn_t
v3d_hub_irq(int irq,void * arg)146 v3d_hub_irq(int irq, void *arg)
147 {
148 struct v3d_dev *v3d = arg;
149 u32 intsts;
150 irqreturn_t status = IRQ_NONE;
151
152 intsts = V3D_READ(V3D_HUB_INT_STS);
153
154 /* Acknowledge the interrupts we're handling here. */
155 V3D_WRITE(V3D_HUB_INT_CLR, intsts);
156
157 if (intsts & V3D_HUB_INT_TFUC) {
158 struct v3d_fence *fence =
159 to_v3d_fence(v3d->tfu_job->base.irq_fence);
160
161 trace_v3d_tfu_irq(&v3d->drm, fence->seqno);
162 dma_fence_signal(&fence->base);
163 v3d->tfu_job = NULL;
164 status = IRQ_HANDLED;
165 }
166
167 if (intsts & (V3D_HUB_INT_MMU_WRV |
168 V3D_HUB_INT_MMU_PTI |
169 V3D_HUB_INT_MMU_CAP)) {
170 u32 axi_id = V3D_READ(V3D_MMU_VIO_ID);
171 u64 vio_addr = ((u64)V3D_READ(V3D_MMU_VIO_ADDR) <<
172 (v3d->va_width - 32));
173 static const char *const v3d41_axi_ids[] = {
174 "L2T",
175 "PTB",
176 "PSE",
177 "TLB",
178 "CLE",
179 "TFU",
180 "MMU",
181 "GMP",
182 };
183 const char *client = "?";
184
185 V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL));
186
187 if (v3d->ver >= 41) {
188 axi_id = axi_id >> 5;
189 if (axi_id < ARRAY_SIZE(v3d41_axi_ids))
190 client = v3d41_axi_ids[axi_id];
191 }
192
193 dev_err(v3d->drm.dev, "MMU error from client %s (%d) at 0x%llx%s%s%s\n",
194 client, axi_id, (long long)vio_addr,
195 ((intsts & V3D_HUB_INT_MMU_WRV) ?
196 ", write violation" : ""),
197 ((intsts & V3D_HUB_INT_MMU_PTI) ?
198 ", pte invalid" : ""),
199 ((intsts & V3D_HUB_INT_MMU_CAP) ?
200 ", cap exceeded" : ""));
201 status = IRQ_HANDLED;
202 }
203
204 return status;
205 }
206
207 int
v3d_irq_init(struct v3d_dev * v3d)208 v3d_irq_init(struct v3d_dev *v3d)
209 {
210 int irq1, ret, core;
211
212 INIT_WORK(&v3d->overflow_mem_work, v3d_overflow_mem_work);
213
214 /* Clear any pending interrupts someone might have left around
215 * for us.
216 */
217 for (core = 0; core < v3d->cores; core++)
218 V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS);
219 V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS);
220
221 irq1 = platform_get_irq_optional(v3d_to_pdev(v3d), 1);
222 if (irq1 == -EPROBE_DEFER)
223 return irq1;
224 if (irq1 > 0) {
225 ret = devm_request_irq(v3d->drm.dev, irq1,
226 v3d_irq, IRQF_SHARED,
227 "v3d_core0", v3d);
228 if (ret)
229 goto fail;
230 ret = devm_request_irq(v3d->drm.dev,
231 platform_get_irq(v3d_to_pdev(v3d), 0),
232 v3d_hub_irq, IRQF_SHARED,
233 "v3d_hub", v3d);
234 if (ret)
235 goto fail;
236 } else {
237 v3d->single_irq_line = true;
238
239 ret = devm_request_irq(v3d->drm.dev,
240 platform_get_irq(v3d_to_pdev(v3d), 0),
241 v3d_irq, IRQF_SHARED,
242 "v3d", v3d);
243 if (ret)
244 goto fail;
245 }
246
247 v3d_irq_enable(v3d);
248 return 0;
249
250 fail:
251 if (ret != -EPROBE_DEFER)
252 dev_err(v3d->drm.dev, "IRQ setup failed: %d\n", ret);
253 return ret;
254 }
255
256 void
v3d_irq_enable(struct v3d_dev * v3d)257 v3d_irq_enable(struct v3d_dev *v3d)
258 {
259 int core;
260
261 /* Enable our set of interrupts, masking out any others. */
262 for (core = 0; core < v3d->cores; core++) {
263 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~V3D_CORE_IRQS);
264 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_CLR, V3D_CORE_IRQS);
265 }
266
267 V3D_WRITE(V3D_HUB_INT_MSK_SET, ~V3D_HUB_IRQS);
268 V3D_WRITE(V3D_HUB_INT_MSK_CLR, V3D_HUB_IRQS);
269 }
270
271 void
v3d_irq_disable(struct v3d_dev * v3d)272 v3d_irq_disable(struct v3d_dev *v3d)
273 {
274 int core;
275
276 /* Disable all interrupts. */
277 for (core = 0; core < v3d->cores; core++)
278 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~0);
279 V3D_WRITE(V3D_HUB_INT_MSK_SET, ~0);
280
281 /* Clear any pending interrupts we might have left. */
282 for (core = 0; core < v3d->cores; core++)
283 V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS);
284 V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS);
285
286 cancel_work_sync(&v3d->overflow_mem_work);
287 }
288
289 /** Reinitializes interrupt registers when a GPU reset is performed. */
v3d_irq_reset(struct v3d_dev * v3d)290 void v3d_irq_reset(struct v3d_dev *v3d)
291 {
292 v3d_irq_enable(v3d);
293 }
294