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Searched defs:input_rate (Results 1 – 22 of 22) sorted by relevance

/openbmc/linux/drivers/clk/mmp/
H A Dclk-pll.c24 unsigned long input_rate; member
104 unsigned long input_rate, in mmp_clk_register_pll()
H A Dclk.h235 unsigned long input_rate; member
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3036.c26 #define RATE_TO_DIV(input_rate, output_rate) \ argument
29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rk3328.c28 #define RATE_TO_DIV(input_rate, output_rate) \ argument
30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rk322x.c26 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rk3128.c27 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rk3188.c71 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rk3368.c41 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rk3399.c40 #define RATE_TO_DIV(input_rate, output_rate) \ argument
42 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rv1108.c29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rk3288.c131 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
/openbmc/u-boot/drivers/clk/aspeed/
H A Dclk_ast2400.c269 ulong input_rate; member
278 static bool ast2400_get_clock_config_default(ulong input_rate, in ast2400_get_clock_config_default()
307 static ulong ast2400_calc_clock_config(ulong input_rate, ulong requested_rate, in ast2400_calc_clock_config()
H A Dclk_ast2500.c243 ulong input_rate; member
252 static bool ast2500_get_clock_config_default(ulong input_rate, in ast2500_get_clock_config_default()
281 static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate, in ast2500_calc_clock_config()
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dclock.h62 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) in clk_get_divisor()
/openbmc/linux/drivers/clk/tegra/
H A Dclk-pll.c959 unsigned long input_rate; in clk_plle_enable() local
1122 unsigned long flags = 0, input_rate; in clk_pllu_enable() local
1254 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate) in tegra_pll_get_fixed_mdiv()
1453 unsigned long input_rate, u32 n) in _pllcx_update_dynamic_coef()
1616 unsigned long input_rate; in clk_plle_tegra114_enable() local
1745 unsigned long flags = 0, input_rate; in clk_pllu_tegra114_enable() local
2455 unsigned long input_rate; in clk_plle_tegra210_enable() local
H A Dclk-tegra210.c1111 unsigned long input_rate; in pllx_get_dyn_steps() local
1480 unsigned long rate, unsigned long input_rate) in tegra210_pll_fixed_mdiv_cfg()
H A Dclk.h165 unsigned long input_rate; member
/openbmc/u-boot/drivers/spi/
H A Drk_spi.c48 uint input_rate; member
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock.c1408 unsigned int fine_scalar_bits, unsigned int input_rate, in clock_calc_best_scalar()
/openbmc/linux/sound/pci/ctxfi/
H A Dctatc.c195 atc_get_pitch(unsigned int input_rate, unsigned int output_rate) in atc_get_pitch()
/openbmc/linux/sound/soc/stm/
H A Dstm32_sai_sub.c313 unsigned long input_rate, in stm32_sai_get_clk_div()
H A Dstm32_i2s.c265 unsigned long input_rate, in stm32_i2s_calc_clk_div()