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Searched defs:dram_info (Results 1 – 23 of 23) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_hw_training.h251 typedef struct dram_info { struct
252 u32 num_cs;
253 u32 cs_ena;
254 u32 num_of_std_pups; /* Q value = ddrWidth/8 - Without ECC!! */
255 u32 num_of_total_pups; /* numOfStdPups + eccEna */
256 u32 target_frequency; /* DDR Frequency */
257 u32 ddr_width; /* 32/64 Bit or 16/32 Bit */
258 u32 ecc_ena; /* 0/1 */
259 u32 wl_val[MAX_CS][MAX_PUP_NUM][7];
260 u32 rl_val[MAX_CS][MAX_PUP_NUM][7];
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H A Dddr3_hw_training.c84 MV_DRAM_INFO dram_info; in ddr3_hw_training() local
484 void ddr3_set_performance_params(MV_DRAM_INFO *dram_info) in ddr3_set_performance_params()
619 int ddr3_load_patterns(MV_DRAM_INFO *dram_info, int resume) in ddr3_load_patterns()
695 void ddr3_save_training(MV_DRAM_INFO *dram_info) in ddr3_save_training()
869 int ddr3_check_if_resume_mode(MV_DRAM_INFO *dram_info, u32 freq) in ddr3_check_if_resume_mode()
913 int ddr3_training_suspend_resume(MV_DRAM_INFO *dram_info) in ddr3_training_suspend_resume()
1045 int ddr3_get_min_max_rl_phase(MV_DRAM_INFO *dram_info, u32 *min, u32 *max, in ddr3_get_min_max_rl_phase()
1085 int ddr3_odt_read_dynamic_config(MV_DRAM_INFO *dram_info) in ddr3_odt_read_dynamic_config()
H A Dddr3_dqs.c92 static u32 *ddr3_dqs_choose_pattern(MV_DRAM_INFO *dram_info, u32 victim_dq) in ddr3_dqs_choose_pattern()
130 int ddr3_dqs_centralization_rx(MV_DRAM_INFO *dram_info) in ddr3_dqs_centralization_rx()
212 int ddr3_dqs_centralization_tx(MV_DRAM_INFO *dram_info) in ddr3_dqs_centralization_tx()
295 int ddr3_find_adll_limits(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc, int is_tx) in ddr3_find_adll_limits()
886 static int ddr3_center_calc(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc, in ddr3_center_calc()
951 int ddr3_special_pattern_i_search(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc, in ddr3_special_pattern_i_search()
1112 int ddr3_special_pattern_ii_search(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc, in ddr3_special_pattern_ii_search()
1261 int ddr3_set_dqs_centralization_results(MV_DRAM_INFO *dram_info, u32 cs, in ddr3_set_dqs_centralization_results()
1327 int ddr3_load_dqs_patterns(MV_DRAM_INFO *dram_info) in ddr3_load_dqs_patterns()
H A Dddr3_pbs.c75 int ddr3_pbs_tx(MV_DRAM_INFO *dram_info) in ddr3_pbs_tx()
404 static int ddr3_tx_shift_dqs_adll_step_before_fail(MV_DRAM_INFO *dram_info, in ddr3_tx_shift_dqs_adll_step_before_fail()
519 int ddr3_pbs_rx(MV_DRAM_INFO *dram_info) in ddr3_pbs_rx()
916 static int ddr3_rx_shift_dqs_to_first_fail(MV_DRAM_INFO *dram_info, u32 cur_pup, in ddr3_rx_shift_dqs_to_first_fail()
1136 static int ddr3_pbs_per_bit(MV_DRAM_INFO *dram_info, int *start_over, int is_tx, in ddr3_pbs_per_bit()
1416 static int ddr3_set_pbs_results(MV_DRAM_INFO *dram_info, int is_tx) in ddr3_set_pbs_results()
1530 int ddr3_load_pbs_patterns(MV_DRAM_INFO *dram_info) in ddr3_load_pbs_patterns()
H A Dddr3_write_leveling.c64 int ddr3_write_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info) in ddr3_write_leveling_hw()
184 int ddr3_wl_supplement(MV_DRAM_INFO *dram_info) in ddr3_wl_supplement()
472 int ddr3_write_leveling_hw_reg_dimm(u32 freq, MV_DRAM_INFO *dram_info) in ddr3_write_leveling_hw_reg_dimm()
657 int ddr3_write_leveling_sw(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info) in ddr3_write_leveling_sw()
882 MV_DRAM_INFO *dram_info) in ddr3_write_leveling_sw_reg_dimm()
1125 u32 *result, MV_DRAM_INFO *dram_info) in ddr3_write_leveling_single_cs()
H A Dddr3_sdram.c163 int ddr3_sdram_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup, in ddr3_sdram_compare()
219 int ddr3_sdram_dm_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup, in ddr3_sdram_dm_compare()
280 int ddr3_sdram_pbs_compare(MV_DRAM_INFO *dram_info, u32 pup_locked, in ddr3_sdram_pbs_compare()
441 int ddr3_sdram_direct_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup, in ddr3_sdram_direct_compare()
599 int ddr3_sdram_dqs_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup, in ddr3_sdram_dqs_compare()
H A Dddr3_read_leveling.c61 int ddr3_read_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info) in ddr3_read_leveling_hw()
179 int ddr3_read_leveling_sw(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info) in ddr3_read_leveling_sw()
401 MV_DRAM_INFO *dram_info) in ddr3_read_leveling_single_cs_rl_mode()
753 MV_DRAM_INFO *dram_info) in ddr3_read_leveling_single_cs_window_mode()
H A Dddr3_dfs.c112 int ddr3_dfs_high_2_low(u32 freq, MV_DRAM_INFO *dram_info) in ddr3_dfs_high_2_low()
768 int ddr3_dfs_low_2_high(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info) in ddr3_dfs_low_2_high()
H A Dxor.c23 void mv_sys_xor_init(MV_DRAM_INFO *dram_info) in mv_sys_xor_init()
/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3328.c14 struct dram_info { struct
21 struct dram_info *priv = dev_get_priv(dev); in rk3328_dmc_probe() argument
H A Dsdram_rk3128.c14 struct dram_info { struct
21 struct dram_info *priv = dev_get_priv(dev); in rk3128_dmc_probe() argument
H A Ddmc-rk3368.c22 struct dram_info { struct
23 struct ram_info info;
24 struct clk ddr_clk;
25 struct rk3368_cru *cru;
26 struct rk3368_grf *grf;
27 struct rk3368_ddr_pctl *pctl;
28 struct rk3368_ddrphy *phy;
29 struct rk3368_pmu_grf *pmugrf;
30 struct rk3368_msch *msch;
H A Dsdram_rk3399.c32 struct dram_info { struct
34 struct chan_info chan[2];
35 struct clk ddr_clk;
36 struct rk3399_cru *cru;
37 struct rk3399_pmucru *pmucru;
38 struct rk3399_pmusgrf_regs *pmusgrf;
39 struct rk3399_ddr_cic_regs *cic;
41 struct ram_info info;
42 struct rk3399_pmugrf_regs *pmugrf;
H A Dsdram_rk3288.c35 struct dram_info { struct
36 struct chan_info chan[2];
37 struct ram_info info;
38 struct clk ddr_clk;
39 struct rk3288_cru *cru;
40 struct rk3288_grf *grf;
41 struct rk3288_sgrf *sgrf;
42 struct rk3288_pmu *pmu;
43 bool is_veyron;
H A Dsdram_rk322x.c32 struct dram_info { struct
33 struct chan_info chan[1];
34 struct ram_info info;
35 struct clk ddr_clk;
36 struct rk322x_cru *cru;
37 struct rk322x_grf *grf;
H A Dsdram_rk3188.c33 struct dram_info { struct
34 struct chan_info chan[1];
35 struct ram_info info;
36 struct clk ddr_clk;
37 struct rk3188_cru *cru;
38 struct rk3188_grf *grf;
39 struct rk3188_sgrf *sgrf;
40 struct rk3188_pmu *pmu;
/openbmc/u-boot/drivers/ram/aspeed/
H A Dsdram_ast2500.c82 struct dram_info { struct
83 struct ram_info info;
84 struct clk ddr_clk;
85 struct ast2500_sdrammc_regs *regs;
109 static void ast2500_ddr_phy_init_process(struct dram_info *info) in ast2500_ddr_phy_init_process() argument
H A Dsdram_ast2600.c195 struct dram_info { struct
206 static void ast2600_sdramphy_kick_training(struct dram_info *info) in ast2600_sdramphy_kick_training() argument
/openbmc/linux/drivers/gpu/drm/i915/soc/
H A Dintel_dram.c337 struct dram_info *dram_info = &i915->dram_info; in skl_dram_get_channels_info() local
400 struct dram_info *dram_info = &i915->dram_info; in skl_get_dram_info() local
494 struct dram_info *dram_info = &i915->dram_info; in bxt_get_dram_info() local
542 struct dram_info *dram_info = &dev_priv->dram_info; in icl_pcode_read_mem_global_info() local
622 struct dram_info *dram_info = &i915->dram_info; in xelpdp_get_dram_info() local
657 struct dram_info *dram_info = &i915->dram_info; in intel_dram_detect() local
/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_drv.h297 struct dram_info { struct
298 bool wm_lv_0_adjust_needed;
299 u8 num_channels;
300 bool symmetric_memory;
301 enum intel_dram_type {
309 } type;
310 u8 num_qgv_points;
311 u8 num_psf_gv_points;
312 } dram_info; member
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-dbg-tlv.c744 struct iwl_dram_info *dram_info) in iwl_dbg_tlv_update_dram()
799 struct iwl_dram_info *dram_info; in iwl_dbg_tlv_update_drams() local
901 struct iwl_dbgc1_info dram_info = {}; in iwl_dbg_tlv_apply_config() local
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_bw.c214 const struct dram_info *dram_info = &dev_priv->dram_info; in icl_get_qgv_points() local
457 const struct dram_info *dram_info = &dev_priv->dram_info; in tgl_get_bw_info() local
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Dtx.h273 struct iwl_dram_sec_info dram_info; member
295 struct iwl_dram_sec_info dram_info; member