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Searched defs:ccsr_scfg (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dimmap_ls102xa.h194 struct ccsr_scfg { struct
195 u32 dpslpcr;
196 u32 resv0[2];
197 u32 etsecclkdpslpcr;
198 u32 resv1[5];
199 u32 fuseovrdcr;
200 u32 pixclkcr;
201 u32 resv2[5];
202 u32 spimsicr;
203 u32 resv3[6];
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dimmap_lsch2.h437 struct ccsr_scfg { struct
438 u8 res_000[0x100-0x000];
439 u32 usb2_icid;
440 u32 usb3_icid;
441 u8 res_108[0x114-0x108];
442 u32 dma_icid;
443 u32 sata_icid;
444 u32 usb1_icid;
445 u32 qe_icid;
446 u32 sdhc_icid;
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dimmap_85xx.h3124 struct ccsr_scfg { struct
3125 u32 dpslpcr; /* 0x000 Deep Sleep Control register */
3126 u32 usb1dpslpcsr;/* 0x004 USB1 Deep Sleep Control Status register */
3127 u32 usb2dpslpcsr;/* 0x008 USB2 Deep Sleep Control Status register */
3128 u32 fmclkdpslpcr;/* 0x00c FM Clock Deep Sleep Control register */
3129 u32 res1[4];
3130 u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control reg */
3131 u32 res2;
3132 u32 pixclkcr; /* 0x028 Pixel Clock Control register */
3133 u32 res3[245];
[all …]