1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11 #include <linux/module.h>
12 #include <linux/ioport.h>
13 #include <linux/init.h>
14 #include <linux/console.h>
15 #include <linux/sysrq.h>
16 #include <linux/platform_device.h>
17 #include <linux/tty.h>
18 #include <linux/tty_flip.h>
19 #include <linux/serial_core.h>
20 #include <linux/serial.h>
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/ktime.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/rational.h>
26 #include <linux/slab.h>
27 #include <linux/of.h>
28 #include <linux/io.h>
29 #include <linux/iopoll.h>
30 #include <linux/dma-mapping.h>
31
32 #include <asm/irq.h>
33 #include <linux/dma/imx-dma.h>
34
35 #include "serial_mctrl_gpio.h"
36
37 /* Register definitions */
38 #define URXD0 0x0 /* Receiver Register */
39 #define URTX0 0x40 /* Transmitter Register */
40 #define UCR1 0x80 /* Control Register 1 */
41 #define UCR2 0x84 /* Control Register 2 */
42 #define UCR3 0x88 /* Control Register 3 */
43 #define UCR4 0x8c /* Control Register 4 */
44 #define UFCR 0x90 /* FIFO Control Register */
45 #define USR1 0x94 /* Status Register 1 */
46 #define USR2 0x98 /* Status Register 2 */
47 #define UESC 0x9c /* Escape Character Register */
48 #define UTIM 0xa0 /* Escape Timer Register */
49 #define UBIR 0xa4 /* BRM Incremental Register */
50 #define UBMR 0xa8 /* BRM Modulator Register */
51 #define UBRC 0xac /* Baud Rate Count Register */
52 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
53 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
54 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
55
56 /* UART Control Register Bit Fields.*/
57 #define URXD_DUMMY_READ (1<<16)
58 #define URXD_CHARRDY (1<<15)
59 #define URXD_ERR (1<<14)
60 #define URXD_OVRRUN (1<<13)
61 #define URXD_FRMERR (1<<12)
62 #define URXD_BRK (1<<11)
63 #define URXD_PRERR (1<<10)
64 #define URXD_RX_DATA (0xFF<<0)
65 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
66 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
67 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
68 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
69 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
70 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
71 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
72 #define UCR1_IREN (1<<7) /* Infrared interface enable */
73 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
74 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
75 #define UCR1_SNDBRK (1<<4) /* Send break */
76 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
77 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
78 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
79 #define UCR1_DOZE (1<<1) /* Doze */
80 #define UCR1_UARTEN (1<<0) /* UART enabled */
81 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
82 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
83 #define UCR2_CTSC (1<<13) /* CTS pin control */
84 #define UCR2_CTS (1<<12) /* Clear to send */
85 #define UCR2_ESCEN (1<<11) /* Escape enable */
86 #define UCR2_PREN (1<<8) /* Parity enable */
87 #define UCR2_PROE (1<<7) /* Parity odd/even */
88 #define UCR2_STPB (1<<6) /* Stop */
89 #define UCR2_WS (1<<5) /* Word size */
90 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
91 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
92 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
93 #define UCR2_RXEN (1<<1) /* Receiver enabled */
94 #define UCR2_SRST (1<<0) /* SW reset */
95 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
96 #define UCR3_PARERREN (1<<12) /* Parity enable */
97 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
98 #define UCR3_DSR (1<<10) /* Data set ready */
99 #define UCR3_DCD (1<<9) /* Data carrier detect */
100 #define UCR3_RI (1<<8) /* Ring indicator */
101 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
102 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
103 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
104 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
105 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
106 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
107 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
108 #define UCR3_BPEN (1<<0) /* Preset registers enable */
109 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
110 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
111 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
112 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
113 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
114 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
115 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
116 #define UCR4_IRSC (1<<5) /* IR special case */
117 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
118 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
119 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
120 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
121 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
122 #define UFCR_RXTL_MASK 0x3F /* Receiver trigger 6 bits wide */
123 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
124 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
125 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
126 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
127 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
128 #define USR1_RTSS (1<<14) /* RTS pin status */
129 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
130 #define USR1_RTSD (1<<12) /* RTS delta */
131 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
132 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
133 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
134 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
135 #define USR1_DTRD (1<<7) /* DTR Delta */
136 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
137 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
138 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
139 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
140 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
141 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
142 #define USR2_IDLE (1<<12) /* Idle condition */
143 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
144 #define USR2_RIIN (1<<9) /* Ring Indicator Input */
145 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
146 #define USR2_WAKE (1<<7) /* Wake */
147 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
148 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
149 #define USR2_TXDC (1<<3) /* Transmitter complete */
150 #define USR2_BRCD (1<<2) /* Break condition */
151 #define USR2_ORE (1<<1) /* Overrun error */
152 #define USR2_RDR (1<<0) /* Recv data ready */
153 #define UTS_FRCPERR (1<<13) /* Force parity error */
154 #define UTS_LOOP (1<<12) /* Loop tx and rx */
155 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
156 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
157 #define UTS_TXFULL (1<<4) /* TxFIFO full */
158 #define UTS_RXFULL (1<<3) /* RxFIFO full */
159 #define UTS_SOFTRST (1<<0) /* Software reset */
160
161 /* We've been assigned a range on the "Low-density serial ports" major */
162 #define SERIAL_IMX_MAJOR 207
163 #define MINOR_START 16
164 #define DEV_NAME "ttymxc"
165
166 /*
167 * This determines how often we check the modem status signals
168 * for any change. They generally aren't connected to an IRQ
169 * so we have to poll them. We also check immediately before
170 * filling the TX fifo incase CTS has been dropped.
171 */
172 #define MCTRL_TIMEOUT (250*HZ/1000)
173
174 #define DRIVER_NAME "IMX-uart"
175
176 #define UART_NR 8
177
178 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
179 enum imx_uart_type {
180 IMX1_UART,
181 IMX21_UART,
182 IMX53_UART,
183 IMX6Q_UART,
184 };
185
186 /* device type dependent stuff */
187 struct imx_uart_data {
188 unsigned uts_reg;
189 enum imx_uart_type devtype;
190 };
191
192 enum imx_tx_state {
193 OFF,
194 WAIT_AFTER_RTS,
195 SEND,
196 WAIT_AFTER_SEND,
197 };
198
199 struct imx_port {
200 struct uart_port port;
201 struct timer_list timer;
202 unsigned int old_status;
203 unsigned int have_rtscts:1;
204 unsigned int have_rtsgpio:1;
205 unsigned int dte_mode:1;
206 unsigned int inverted_tx:1;
207 unsigned int inverted_rx:1;
208 struct clk *clk_ipg;
209 struct clk *clk_per;
210 const struct imx_uart_data *devdata;
211
212 struct mctrl_gpios *gpios;
213
214 /* counter to stop 0xff flood */
215 int idle_counter;
216
217 /* DMA fields */
218 unsigned int dma_is_enabled:1;
219 unsigned int dma_is_rxing:1;
220 unsigned int dma_is_txing:1;
221 struct dma_chan *dma_chan_rx, *dma_chan_tx;
222 struct scatterlist rx_sgl, tx_sgl[2];
223 void *rx_buf;
224 struct circ_buf rx_ring;
225 unsigned int rx_buf_size;
226 unsigned int rx_period_length;
227 unsigned int rx_periods;
228 dma_cookie_t rx_cookie;
229 unsigned int tx_bytes;
230 unsigned int dma_tx_nents;
231 unsigned int saved_reg[10];
232 bool context_saved;
233
234 enum imx_tx_state tx_state;
235 struct hrtimer trigger_start_tx;
236 struct hrtimer trigger_stop_tx;
237 unsigned int rxtl;
238 };
239
240 struct imx_port_ucrs {
241 unsigned int ucr1;
242 unsigned int ucr2;
243 unsigned int ucr3;
244 };
245
246 static struct imx_uart_data imx_uart_devdata[] = {
247 [IMX1_UART] = {
248 .uts_reg = IMX1_UTS,
249 .devtype = IMX1_UART,
250 },
251 [IMX21_UART] = {
252 .uts_reg = IMX21_UTS,
253 .devtype = IMX21_UART,
254 },
255 [IMX53_UART] = {
256 .uts_reg = IMX21_UTS,
257 .devtype = IMX53_UART,
258 },
259 [IMX6Q_UART] = {
260 .uts_reg = IMX21_UTS,
261 .devtype = IMX6Q_UART,
262 },
263 };
264
265 static const struct of_device_id imx_uart_dt_ids[] = {
266 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
267 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
268 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
269 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
270 { /* sentinel */ }
271 };
272 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
273
imx_uart_writel(struct imx_port * sport,u32 val,u32 offset)274 static inline void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
275 {
276 writel(val, sport->port.membase + offset);
277 }
278
imx_uart_readl(struct imx_port * sport,u32 offset)279 static inline u32 imx_uart_readl(struct imx_port *sport, u32 offset)
280 {
281 return readl(sport->port.membase + offset);
282 }
283
imx_uart_uts_reg(struct imx_port * sport)284 static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
285 {
286 return sport->devdata->uts_reg;
287 }
288
imx_uart_is_imx1(struct imx_port * sport)289 static inline int imx_uart_is_imx1(struct imx_port *sport)
290 {
291 return sport->devdata->devtype == IMX1_UART;
292 }
293
294 /*
295 * Save and restore functions for UCR1, UCR2 and UCR3 registers
296 */
297 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_ucrs_save(struct imx_port * sport,struct imx_port_ucrs * ucr)298 static void imx_uart_ucrs_save(struct imx_port *sport,
299 struct imx_port_ucrs *ucr)
300 {
301 /* save control registers */
302 ucr->ucr1 = imx_uart_readl(sport, UCR1);
303 ucr->ucr2 = imx_uart_readl(sport, UCR2);
304 ucr->ucr3 = imx_uart_readl(sport, UCR3);
305 }
306
imx_uart_ucrs_restore(struct imx_port * sport,struct imx_port_ucrs * ucr)307 static void imx_uart_ucrs_restore(struct imx_port *sport,
308 struct imx_port_ucrs *ucr)
309 {
310 /* restore control registers */
311 imx_uart_writel(sport, ucr->ucr1, UCR1);
312 imx_uart_writel(sport, ucr->ucr2, UCR2);
313 imx_uart_writel(sport, ucr->ucr3, UCR3);
314 }
315 #endif
316
317 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_active(struct imx_port * sport,u32 * ucr2)318 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
319 {
320 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
321
322 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
323 }
324
325 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_inactive(struct imx_port * sport,u32 * ucr2)326 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
327 {
328 *ucr2 &= ~UCR2_CTSC;
329 *ucr2 |= UCR2_CTS;
330
331 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
332 }
333
start_hrtimer_ms(struct hrtimer * hrt,unsigned long msec)334 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
335 {
336 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
337 }
338
339 /* called with port.lock taken and irqs off */
imx_uart_soft_reset(struct imx_port * sport)340 static void imx_uart_soft_reset(struct imx_port *sport)
341 {
342 int i = 10;
343 u32 ucr2, ubir, ubmr, uts;
344
345 /*
346 * According to the Reference Manual description of the UART SRST bit:
347 *
348 * "Reset the transmit and receive state machines,
349 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
350 * and UTS[6-3]".
351 *
352 * We don't need to restore the old values from USR1, USR2, URXD and
353 * UTXD. UBRC is read only, so only save/restore the other three
354 * registers.
355 */
356 ubir = imx_uart_readl(sport, UBIR);
357 ubmr = imx_uart_readl(sport, UBMR);
358 uts = imx_uart_readl(sport, IMX21_UTS);
359
360 ucr2 = imx_uart_readl(sport, UCR2);
361 imx_uart_writel(sport, ucr2 & ~UCR2_SRST, UCR2);
362
363 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
364 udelay(1);
365
366 /* Restore the registers */
367 imx_uart_writel(sport, ubir, UBIR);
368 imx_uart_writel(sport, ubmr, UBMR);
369 imx_uart_writel(sport, uts, IMX21_UTS);
370
371 sport->idle_counter = 0;
372 }
373
imx_uart_disable_loopback_rs485(struct imx_port * sport)374 static void imx_uart_disable_loopback_rs485(struct imx_port *sport)
375 {
376 unsigned int uts;
377
378 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
379 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
380 uts &= ~UTS_LOOP;
381 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
382 }
383
384 /* called with port.lock taken and irqs off */
imx_uart_start_rx(struct uart_port * port)385 static void imx_uart_start_rx(struct uart_port *port)
386 {
387 struct imx_port *sport = (struct imx_port *)port;
388 unsigned int ucr1, ucr2;
389
390 ucr1 = imx_uart_readl(sport, UCR1);
391 ucr2 = imx_uart_readl(sport, UCR2);
392
393 ucr2 |= UCR2_RXEN;
394
395 if (sport->dma_is_enabled) {
396 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
397 } else {
398 ucr1 |= UCR1_RRDYEN;
399 ucr2 |= UCR2_ATEN;
400 }
401
402 /* Write UCR2 first as it includes RXEN */
403 imx_uart_writel(sport, ucr2, UCR2);
404 imx_uart_writel(sport, ucr1, UCR1);
405 imx_uart_disable_loopback_rs485(sport);
406 }
407
408 /* called with port.lock taken and irqs off */
imx_uart_stop_tx(struct uart_port * port)409 static void imx_uart_stop_tx(struct uart_port *port)
410 {
411 struct imx_port *sport = (struct imx_port *)port;
412 u32 ucr1, ucr4, usr2;
413
414 if (sport->tx_state == OFF)
415 return;
416
417 /*
418 * We are maybe in the SMP context, so if the DMA TX thread is running
419 * on other cpu, we have to wait for it to finish.
420 */
421 if (sport->dma_is_txing)
422 return;
423
424 ucr1 = imx_uart_readl(sport, UCR1);
425 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
426
427 ucr4 = imx_uart_readl(sport, UCR4);
428 usr2 = imx_uart_readl(sport, USR2);
429 if ((!(usr2 & USR2_TXDC)) && (ucr4 & UCR4_TCEN)) {
430 /* The shifter is still busy, so retry once TC triggers */
431 return;
432 }
433
434 ucr4 &= ~UCR4_TCEN;
435 imx_uart_writel(sport, ucr4, UCR4);
436
437 /* in rs485 mode disable transmitter */
438 if (port->rs485.flags & SER_RS485_ENABLED) {
439 if (sport->tx_state == SEND) {
440 sport->tx_state = WAIT_AFTER_SEND;
441
442 if (port->rs485.delay_rts_after_send > 0) {
443 start_hrtimer_ms(&sport->trigger_stop_tx,
444 port->rs485.delay_rts_after_send);
445 return;
446 }
447
448 /* continue without any delay */
449 }
450
451 if (sport->tx_state == WAIT_AFTER_RTS ||
452 sport->tx_state == WAIT_AFTER_SEND) {
453 u32 ucr2;
454
455 hrtimer_try_to_cancel(&sport->trigger_start_tx);
456
457 ucr2 = imx_uart_readl(sport, UCR2);
458 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
459 imx_uart_rts_active(sport, &ucr2);
460 else
461 imx_uart_rts_inactive(sport, &ucr2);
462 imx_uart_writel(sport, ucr2, UCR2);
463
464 if (!port->rs485_rx_during_tx_gpio)
465 imx_uart_start_rx(port);
466
467 sport->tx_state = OFF;
468 }
469 } else {
470 sport->tx_state = OFF;
471 }
472 }
473
imx_uart_stop_rx_with_loopback_ctrl(struct uart_port * port,bool loopback)474 static void imx_uart_stop_rx_with_loopback_ctrl(struct uart_port *port, bool loopback)
475 {
476 struct imx_port *sport = (struct imx_port *)port;
477 u32 ucr1, ucr2, ucr4, uts;
478
479 ucr1 = imx_uart_readl(sport, UCR1);
480 ucr2 = imx_uart_readl(sport, UCR2);
481 ucr4 = imx_uart_readl(sport, UCR4);
482
483 if (sport->dma_is_enabled) {
484 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
485 } else {
486 ucr1 &= ~UCR1_RRDYEN;
487 ucr2 &= ~UCR2_ATEN;
488 ucr4 &= ~UCR4_OREN;
489 }
490 imx_uart_writel(sport, ucr1, UCR1);
491 imx_uart_writel(sport, ucr4, UCR4);
492
493 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
494 if (port->rs485.flags & SER_RS485_ENABLED &&
495 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
496 sport->have_rtscts && !sport->have_rtsgpio && loopback) {
497 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
498 uts |= UTS_LOOP;
499 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
500 ucr2 |= UCR2_RXEN;
501 } else {
502 ucr2 &= ~UCR2_RXEN;
503 }
504
505 imx_uart_writel(sport, ucr2, UCR2);
506 }
507
508 /* called with port.lock taken and irqs off */
imx_uart_stop_rx(struct uart_port * port)509 static void imx_uart_stop_rx(struct uart_port *port)
510 {
511 /*
512 * Stop RX and enable loopback in order to make sure RS485 bus
513 * is not blocked. Se comment in imx_uart_probe().
514 */
515 imx_uart_stop_rx_with_loopback_ctrl(port, true);
516 }
517
518 /* called with port.lock taken and irqs off */
imx_uart_enable_ms(struct uart_port * port)519 static void imx_uart_enable_ms(struct uart_port *port)
520 {
521 struct imx_port *sport = (struct imx_port *)port;
522
523 mod_timer(&sport->timer, jiffies);
524
525 mctrl_gpio_enable_ms(sport->gpios);
526 }
527
528 static void imx_uart_dma_tx(struct imx_port *sport);
529
530 /* called with port.lock taken and irqs off */
imx_uart_transmit_buffer(struct imx_port * sport)531 static inline void imx_uart_transmit_buffer(struct imx_port *sport)
532 {
533 struct circ_buf *xmit = &sport->port.state->xmit;
534
535 if (sport->port.x_char) {
536 /* Send next char */
537 imx_uart_writel(sport, sport->port.x_char, URTX0);
538 sport->port.icount.tx++;
539 sport->port.x_char = 0;
540 return;
541 }
542
543 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
544 imx_uart_stop_tx(&sport->port);
545 return;
546 }
547
548 if (sport->dma_is_enabled) {
549 u32 ucr1;
550 /*
551 * We've just sent a X-char Ensure the TX DMA is enabled
552 * and the TX IRQ is disabled.
553 **/
554 ucr1 = imx_uart_readl(sport, UCR1);
555 ucr1 &= ~UCR1_TRDYEN;
556 if (sport->dma_is_txing) {
557 ucr1 |= UCR1_TXDMAEN;
558 imx_uart_writel(sport, ucr1, UCR1);
559 } else {
560 imx_uart_writel(sport, ucr1, UCR1);
561 imx_uart_dma_tx(sport);
562 }
563
564 return;
565 }
566
567 while (!uart_circ_empty(xmit) &&
568 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
569 /* send xmit->buf[xmit->tail]
570 * out the port here */
571 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
572 uart_xmit_advance(&sport->port, 1);
573 }
574
575 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
576 uart_write_wakeup(&sport->port);
577
578 if (uart_circ_empty(xmit))
579 imx_uart_stop_tx(&sport->port);
580 }
581
imx_uart_dma_tx_callback(void * data)582 static void imx_uart_dma_tx_callback(void *data)
583 {
584 struct imx_port *sport = data;
585 struct scatterlist *sgl = &sport->tx_sgl[0];
586 struct circ_buf *xmit = &sport->port.state->xmit;
587 unsigned long flags;
588 u32 ucr1;
589
590 spin_lock_irqsave(&sport->port.lock, flags);
591
592 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
593
594 ucr1 = imx_uart_readl(sport, UCR1);
595 ucr1 &= ~UCR1_TXDMAEN;
596 imx_uart_writel(sport, ucr1, UCR1);
597
598 uart_xmit_advance(&sport->port, sport->tx_bytes);
599
600 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
601
602 sport->dma_is_txing = 0;
603
604 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
605 uart_write_wakeup(&sport->port);
606
607 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
608 imx_uart_dma_tx(sport);
609 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
610 u32 ucr4 = imx_uart_readl(sport, UCR4);
611 ucr4 |= UCR4_TCEN;
612 imx_uart_writel(sport, ucr4, UCR4);
613 }
614
615 spin_unlock_irqrestore(&sport->port.lock, flags);
616 }
617
618 /* called with port.lock taken and irqs off */
imx_uart_dma_tx(struct imx_port * sport)619 static void imx_uart_dma_tx(struct imx_port *sport)
620 {
621 struct circ_buf *xmit = &sport->port.state->xmit;
622 struct scatterlist *sgl = sport->tx_sgl;
623 struct dma_async_tx_descriptor *desc;
624 struct dma_chan *chan = sport->dma_chan_tx;
625 struct device *dev = sport->port.dev;
626 u32 ucr1, ucr4;
627 int ret;
628
629 if (sport->dma_is_txing)
630 return;
631
632 ucr4 = imx_uart_readl(sport, UCR4);
633 ucr4 &= ~UCR4_TCEN;
634 imx_uart_writel(sport, ucr4, UCR4);
635
636 sport->tx_bytes = uart_circ_chars_pending(xmit);
637
638 if (xmit->tail < xmit->head || xmit->head == 0) {
639 sport->dma_tx_nents = 1;
640 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
641 } else {
642 sport->dma_tx_nents = 2;
643 sg_init_table(sgl, 2);
644 sg_set_buf(sgl, xmit->buf + xmit->tail,
645 UART_XMIT_SIZE - xmit->tail);
646 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
647 }
648
649 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
650 if (ret == 0) {
651 dev_err(dev, "DMA mapping error for TX.\n");
652 return;
653 }
654 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
655 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
656 if (!desc) {
657 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
658 DMA_TO_DEVICE);
659 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
660 return;
661 }
662 desc->callback = imx_uart_dma_tx_callback;
663 desc->callback_param = sport;
664
665 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
666 uart_circ_chars_pending(xmit));
667
668 ucr1 = imx_uart_readl(sport, UCR1);
669 ucr1 |= UCR1_TXDMAEN;
670 imx_uart_writel(sport, ucr1, UCR1);
671
672 /* fire it */
673 sport->dma_is_txing = 1;
674 dmaengine_submit(desc);
675 dma_async_issue_pending(chan);
676 return;
677 }
678
679 /* called with port.lock taken and irqs off */
imx_uart_start_tx(struct uart_port * port)680 static void imx_uart_start_tx(struct uart_port *port)
681 {
682 struct imx_port *sport = (struct imx_port *)port;
683 u32 ucr1;
684
685 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
686 return;
687
688 /*
689 * We cannot simply do nothing here if sport->tx_state == SEND already
690 * because UCR1_TXMPTYEN might already have been cleared in
691 * imx_uart_stop_tx(), but tx_state is still SEND.
692 */
693
694 if (port->rs485.flags & SER_RS485_ENABLED) {
695 if (sport->tx_state == OFF) {
696 u32 ucr2 = imx_uart_readl(sport, UCR2);
697 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
698 imx_uart_rts_active(sport, &ucr2);
699 else
700 imx_uart_rts_inactive(sport, &ucr2);
701 imx_uart_writel(sport, ucr2, UCR2);
702
703 /*
704 * Since we are about to transmit we can not stop RX
705 * with loopback enabled because that will make our
706 * transmitted data being just looped to RX.
707 */
708 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) &&
709 !port->rs485_rx_during_tx_gpio)
710 imx_uart_stop_rx_with_loopback_ctrl(port, false);
711
712 sport->tx_state = WAIT_AFTER_RTS;
713
714 if (port->rs485.delay_rts_before_send > 0) {
715 start_hrtimer_ms(&sport->trigger_start_tx,
716 port->rs485.delay_rts_before_send);
717 return;
718 }
719
720 /* continue without any delay */
721 }
722
723 if (sport->tx_state == WAIT_AFTER_SEND
724 || sport->tx_state == WAIT_AFTER_RTS) {
725
726 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
727
728 /*
729 * Enable transmitter and shifter empty irq only if DMA
730 * is off. In the DMA case this is done in the
731 * tx-callback.
732 */
733 if (!sport->dma_is_enabled) {
734 u32 ucr4 = imx_uart_readl(sport, UCR4);
735 ucr4 |= UCR4_TCEN;
736 imx_uart_writel(sport, ucr4, UCR4);
737 }
738
739 sport->tx_state = SEND;
740 }
741 } else {
742 sport->tx_state = SEND;
743 }
744
745 if (!sport->dma_is_enabled) {
746 ucr1 = imx_uart_readl(sport, UCR1);
747 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
748 }
749
750 if (sport->dma_is_enabled) {
751 if (sport->port.x_char) {
752 /* We have X-char to send, so enable TX IRQ and
753 * disable TX DMA to let TX interrupt to send X-char */
754 ucr1 = imx_uart_readl(sport, UCR1);
755 ucr1 &= ~UCR1_TXDMAEN;
756 ucr1 |= UCR1_TRDYEN;
757 imx_uart_writel(sport, ucr1, UCR1);
758 return;
759 }
760
761 if (!uart_circ_empty(&port->state->xmit) &&
762 !uart_tx_stopped(port))
763 imx_uart_dma_tx(sport);
764 return;
765 }
766 }
767
__imx_uart_rtsint(int irq,void * dev_id)768 static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
769 {
770 struct imx_port *sport = dev_id;
771 u32 usr1;
772
773 imx_uart_writel(sport, USR1_RTSD, USR1);
774 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
775 /*
776 * Update sport->old_status here, so any follow-up calls to
777 * imx_uart_mctrl_check() will be able to recognize that RTS
778 * state changed since last imx_uart_mctrl_check() call.
779 *
780 * In case RTS has been detected as asserted here and later on
781 * deasserted by the time imx_uart_mctrl_check() was called,
782 * imx_uart_mctrl_check() can detect the RTS state change and
783 * trigger uart_handle_cts_change() to unblock the port for
784 * further TX transfers.
785 */
786 if (usr1 & USR1_RTSS)
787 sport->old_status |= TIOCM_CTS;
788 else
789 sport->old_status &= ~TIOCM_CTS;
790 uart_handle_cts_change(&sport->port, usr1);
791 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
792
793 return IRQ_HANDLED;
794 }
795
imx_uart_rtsint(int irq,void * dev_id)796 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
797 {
798 struct imx_port *sport = dev_id;
799 irqreturn_t ret;
800
801 spin_lock(&sport->port.lock);
802
803 ret = __imx_uart_rtsint(irq, dev_id);
804
805 spin_unlock(&sport->port.lock);
806
807 return ret;
808 }
809
imx_uart_txint(int irq,void * dev_id)810 static irqreturn_t imx_uart_txint(int irq, void *dev_id)
811 {
812 struct imx_port *sport = dev_id;
813
814 spin_lock(&sport->port.lock);
815 imx_uart_transmit_buffer(sport);
816 spin_unlock(&sport->port.lock);
817 return IRQ_HANDLED;
818 }
819
820 /* Check if hardware Rx flood is in progress, and issue soft reset to stop it.
821 * This is to be called from Rx ISRs only when some bytes were actually
822 * received.
823 *
824 * A way to reproduce the flood (checked on iMX6SX) is: open iMX UART at 9600
825 * 8N1, and from external source send 0xf0 char at 115200 8N1. In about 90% of
826 * cases this starts a flood of "receiving" of 0xff characters by the iMX6 UART
827 * that is terminated by any activity on RxD line, or could be stopped by
828 * issuing soft reset to the UART (just stop/start of RX does not help). Note
829 * that what we do here is sending isolated start bit about 2.4 times shorter
830 * than it is to be on UART configured baud rate.
831 */
imx_uart_check_flood(struct imx_port * sport,u32 usr2)832 static void imx_uart_check_flood(struct imx_port *sport, u32 usr2)
833 {
834 /* To detect hardware 0xff flood we monitor RxD line between RX
835 * interrupts to isolate "receiving" of char(s) with no activity
836 * on RxD line, that'd never happen on actual data transfers.
837 *
838 * We use USR2_WAKE bit to check for activity on RxD line, but we have a
839 * race here if we clear USR2_WAKE when receiving of a char is in
840 * progress, so we might get RX interrupt later with USR2_WAKE bit
841 * cleared. Note though that as we don't try to clear USR2_WAKE when we
842 * detected no activity, this race may hide actual activity only once.
843 *
844 * Yet another case where receive interrupt may occur without RxD
845 * activity is expiration of aging timer, so we consider this as well.
846 *
847 * We use 'idle_counter' to ensure that we got at least so many RX
848 * interrupts without any detected activity on RxD line. 2 cases
849 * described plus 1 to be on the safe side gives us a margin of 3,
850 * below. In practice I was not able to produce a false positive to
851 * induce soft reset at regular data transfers even using 1 as the
852 * margin, so 3 is actually very strong.
853 *
854 * We count interrupts, not chars in 'idle-counter' for simplicity.
855 */
856
857 if (usr2 & USR2_WAKE) {
858 imx_uart_writel(sport, USR2_WAKE, USR2);
859 sport->idle_counter = 0;
860 } else if (++sport->idle_counter > 3) {
861 dev_warn(sport->port.dev, "RX flood detected: soft reset.");
862 imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */
863 }
864 }
865
__imx_uart_rxint(int irq,void * dev_id)866 static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
867 {
868 struct imx_port *sport = dev_id;
869 struct tty_port *port = &sport->port.state->port;
870 u32 usr2, rx;
871
872 /* If we received something, check for 0xff flood */
873 usr2 = imx_uart_readl(sport, USR2);
874 if (usr2 & USR2_RDR)
875 imx_uart_check_flood(sport, usr2);
876
877 while ((rx = imx_uart_readl(sport, URXD0)) & URXD_CHARRDY) {
878 unsigned int flg = TTY_NORMAL;
879 sport->port.icount.rx++;
880
881 if (unlikely(rx & URXD_ERR)) {
882 if (rx & URXD_BRK) {
883 sport->port.icount.brk++;
884 if (uart_handle_break(&sport->port))
885 continue;
886 }
887 else if (rx & URXD_PRERR)
888 sport->port.icount.parity++;
889 else if (rx & URXD_FRMERR)
890 sport->port.icount.frame++;
891 if (rx & URXD_OVRRUN)
892 sport->port.icount.overrun++;
893
894 if (rx & sport->port.ignore_status_mask)
895 continue;
896
897 rx &= (sport->port.read_status_mask | 0xFF);
898
899 if (rx & URXD_BRK)
900 flg = TTY_BREAK;
901 else if (rx & URXD_PRERR)
902 flg = TTY_PARITY;
903 else if (rx & URXD_FRMERR)
904 flg = TTY_FRAME;
905 if (rx & URXD_OVRRUN)
906 flg = TTY_OVERRUN;
907
908 sport->port.sysrq = 0;
909 } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) {
910 continue;
911 }
912
913 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
914 continue;
915
916 if (tty_insert_flip_char(port, rx, flg) == 0)
917 sport->port.icount.buf_overrun++;
918 }
919
920 tty_flip_buffer_push(port);
921
922 return IRQ_HANDLED;
923 }
924
imx_uart_rxint(int irq,void * dev_id)925 static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
926 {
927 struct imx_port *sport = dev_id;
928 irqreturn_t ret;
929
930 spin_lock(&sport->port.lock);
931
932 ret = __imx_uart_rxint(irq, dev_id);
933
934 spin_unlock(&sport->port.lock);
935
936 return ret;
937 }
938
939 static void imx_uart_clear_rx_errors(struct imx_port *sport);
940
941 /*
942 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
943 */
imx_uart_get_hwmctrl(struct imx_port * sport)944 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
945 {
946 unsigned int tmp = TIOCM_DSR;
947 unsigned usr1 = imx_uart_readl(sport, USR1);
948 unsigned usr2 = imx_uart_readl(sport, USR2);
949
950 if (usr1 & USR1_RTSS)
951 tmp |= TIOCM_CTS;
952
953 /* in DCE mode DCDIN is always 0 */
954 if (!(usr2 & USR2_DCDIN))
955 tmp |= TIOCM_CAR;
956
957 if (sport->dte_mode)
958 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
959 tmp |= TIOCM_RI;
960
961 return tmp;
962 }
963
964 /*
965 * Handle any change of modem status signal since we were last called.
966 */
imx_uart_mctrl_check(struct imx_port * sport)967 static void imx_uart_mctrl_check(struct imx_port *sport)
968 {
969 unsigned int status, changed;
970
971 status = imx_uart_get_hwmctrl(sport);
972 changed = status ^ sport->old_status;
973
974 if (changed == 0)
975 return;
976
977 sport->old_status = status;
978
979 if (changed & TIOCM_RI && status & TIOCM_RI)
980 sport->port.icount.rng++;
981 if (changed & TIOCM_DSR)
982 sport->port.icount.dsr++;
983 if (changed & TIOCM_CAR)
984 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
985 if (changed & TIOCM_CTS)
986 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
987
988 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
989 }
990
imx_uart_int(int irq,void * dev_id)991 static irqreturn_t imx_uart_int(int irq, void *dev_id)
992 {
993 struct imx_port *sport = dev_id;
994 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
995 irqreturn_t ret = IRQ_NONE;
996
997 spin_lock(&sport->port.lock);
998
999 usr1 = imx_uart_readl(sport, USR1);
1000 usr2 = imx_uart_readl(sport, USR2);
1001 ucr1 = imx_uart_readl(sport, UCR1);
1002 ucr2 = imx_uart_readl(sport, UCR2);
1003 ucr3 = imx_uart_readl(sport, UCR3);
1004 ucr4 = imx_uart_readl(sport, UCR4);
1005
1006 /*
1007 * Even if a condition is true that can trigger an irq only handle it if
1008 * the respective irq source is enabled. This prevents some undesired
1009 * actions, for example if a character that sits in the RX FIFO and that
1010 * should be fetched via DMA is tried to be fetched using PIO. Or the
1011 * receiver is currently off and so reading from URXD0 results in an
1012 * exception. So just mask the (raw) status bits for disabled irqs.
1013 */
1014 if ((ucr1 & UCR1_RRDYEN) == 0)
1015 usr1 &= ~USR1_RRDY;
1016 if ((ucr2 & UCR2_ATEN) == 0)
1017 usr1 &= ~USR1_AGTIM;
1018 if ((ucr1 & UCR1_TRDYEN) == 0)
1019 usr1 &= ~USR1_TRDY;
1020 if ((ucr4 & UCR4_TCEN) == 0)
1021 usr2 &= ~USR2_TXDC;
1022 if ((ucr3 & UCR3_DTRDEN) == 0)
1023 usr1 &= ~USR1_DTRD;
1024 if ((ucr1 & UCR1_RTSDEN) == 0)
1025 usr1 &= ~USR1_RTSD;
1026 if ((ucr3 & UCR3_AWAKEN) == 0)
1027 usr1 &= ~USR1_AWAKE;
1028 if ((ucr4 & UCR4_OREN) == 0)
1029 usr2 &= ~USR2_ORE;
1030
1031 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
1032 imx_uart_writel(sport, USR1_AGTIM, USR1);
1033
1034 __imx_uart_rxint(irq, dev_id);
1035 ret = IRQ_HANDLED;
1036 }
1037
1038 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
1039 imx_uart_transmit_buffer(sport);
1040 ret = IRQ_HANDLED;
1041 }
1042
1043 if (usr1 & USR1_DTRD) {
1044 imx_uart_writel(sport, USR1_DTRD, USR1);
1045
1046 imx_uart_mctrl_check(sport);
1047
1048 ret = IRQ_HANDLED;
1049 }
1050
1051 if (usr1 & USR1_RTSD) {
1052 __imx_uart_rtsint(irq, dev_id);
1053 ret = IRQ_HANDLED;
1054 }
1055
1056 if (usr1 & USR1_AWAKE) {
1057 imx_uart_writel(sport, USR1_AWAKE, USR1);
1058 ret = IRQ_HANDLED;
1059 }
1060
1061 if (usr2 & USR2_ORE) {
1062 sport->port.icount.overrun++;
1063 imx_uart_writel(sport, USR2_ORE, USR2);
1064 ret = IRQ_HANDLED;
1065 }
1066
1067 spin_unlock(&sport->port.lock);
1068
1069 return ret;
1070 }
1071
1072 /*
1073 * Return TIOCSER_TEMT when transmitter is not busy.
1074 */
imx_uart_tx_empty(struct uart_port * port)1075 static unsigned int imx_uart_tx_empty(struct uart_port *port)
1076 {
1077 struct imx_port *sport = (struct imx_port *)port;
1078 unsigned int ret;
1079
1080 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1081
1082 /* If the TX DMA is working, return 0. */
1083 if (sport->dma_is_txing)
1084 ret = 0;
1085
1086 return ret;
1087 }
1088
1089 /* called with port.lock taken and irqs off */
imx_uart_get_mctrl(struct uart_port * port)1090 static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1091 {
1092 struct imx_port *sport = (struct imx_port *)port;
1093 unsigned int ret = imx_uart_get_hwmctrl(sport);
1094
1095 mctrl_gpio_get(sport->gpios, &ret);
1096
1097 return ret;
1098 }
1099
1100 /* called with port.lock taken and irqs off */
imx_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)1101 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1102 {
1103 struct imx_port *sport = (struct imx_port *)port;
1104 u32 ucr3, uts;
1105
1106 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1107 u32 ucr2;
1108
1109 /*
1110 * Turn off autoRTS if RTS is lowered and restore autoRTS
1111 * setting if RTS is raised.
1112 */
1113 ucr2 = imx_uart_readl(sport, UCR2);
1114 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1115 if (mctrl & TIOCM_RTS) {
1116 ucr2 |= UCR2_CTS;
1117 /*
1118 * UCR2_IRTS is unset if and only if the port is
1119 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1120 * to get the state to restore to.
1121 */
1122 if (!(ucr2 & UCR2_IRTS))
1123 ucr2 |= UCR2_CTSC;
1124 }
1125 imx_uart_writel(sport, ucr2, UCR2);
1126 }
1127
1128 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1129 if (!(mctrl & TIOCM_DTR))
1130 ucr3 |= UCR3_DSR;
1131 imx_uart_writel(sport, ucr3, UCR3);
1132
1133 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1134 if (mctrl & TIOCM_LOOP)
1135 uts |= UTS_LOOP;
1136 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1137
1138 mctrl_gpio_set(sport->gpios, mctrl);
1139 }
1140
1141 /*
1142 * Interrupts always disabled.
1143 */
imx_uart_break_ctl(struct uart_port * port,int break_state)1144 static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1145 {
1146 struct imx_port *sport = (struct imx_port *)port;
1147 unsigned long flags;
1148 u32 ucr1;
1149
1150 spin_lock_irqsave(&sport->port.lock, flags);
1151
1152 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1153
1154 if (break_state != 0)
1155 ucr1 |= UCR1_SNDBRK;
1156
1157 imx_uart_writel(sport, ucr1, UCR1);
1158
1159 spin_unlock_irqrestore(&sport->port.lock, flags);
1160 }
1161
1162 /*
1163 * This is our per-port timeout handler, for checking the
1164 * modem status signals.
1165 */
imx_uart_timeout(struct timer_list * t)1166 static void imx_uart_timeout(struct timer_list *t)
1167 {
1168 struct imx_port *sport = from_timer(sport, t, timer);
1169 unsigned long flags;
1170
1171 if (sport->port.state) {
1172 spin_lock_irqsave(&sport->port.lock, flags);
1173 imx_uart_mctrl_check(sport);
1174 spin_unlock_irqrestore(&sport->port.lock, flags);
1175
1176 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1177 }
1178 }
1179
1180 /*
1181 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1182 * [1] the RX DMA buffer is full.
1183 * [2] the aging timer expires
1184 *
1185 * Condition [2] is triggered when a character has been sitting in the FIFO
1186 * for at least 8 byte durations.
1187 */
imx_uart_dma_rx_callback(void * data)1188 static void imx_uart_dma_rx_callback(void *data)
1189 {
1190 struct imx_port *sport = data;
1191 struct dma_chan *chan = sport->dma_chan_rx;
1192 struct scatterlist *sgl = &sport->rx_sgl;
1193 struct tty_port *port = &sport->port.state->port;
1194 struct dma_tx_state state;
1195 struct circ_buf *rx_ring = &sport->rx_ring;
1196 enum dma_status status;
1197 unsigned int w_bytes = 0;
1198 unsigned int r_bytes;
1199 unsigned int bd_size;
1200
1201 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1202
1203 if (status == DMA_ERROR) {
1204 spin_lock(&sport->port.lock);
1205 imx_uart_clear_rx_errors(sport);
1206 spin_unlock(&sport->port.lock);
1207 return;
1208 }
1209
1210 /*
1211 * The state-residue variable represents the empty space
1212 * relative to the entire buffer. Taking this in consideration
1213 * the head is always calculated base on the buffer total
1214 * length - DMA transaction residue. The UART script from the
1215 * SDMA firmware will jump to the next buffer descriptor,
1216 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1217 * Taking this in consideration the tail is always at the
1218 * beginning of the buffer descriptor that contains the head.
1219 */
1220
1221 /* Calculate the head */
1222 rx_ring->head = sg_dma_len(sgl) - state.residue;
1223
1224 /* Calculate the tail. */
1225 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1226 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1227
1228 if (rx_ring->head <= sg_dma_len(sgl) &&
1229 rx_ring->head > rx_ring->tail) {
1230
1231 /* Move data from tail to head */
1232 r_bytes = rx_ring->head - rx_ring->tail;
1233
1234 /* If we received something, check for 0xff flood */
1235 spin_lock(&sport->port.lock);
1236 imx_uart_check_flood(sport, imx_uart_readl(sport, USR2));
1237 spin_unlock(&sport->port.lock);
1238
1239 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1240
1241 /* CPU claims ownership of RX DMA buffer */
1242 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1243 DMA_FROM_DEVICE);
1244
1245 w_bytes = tty_insert_flip_string(port,
1246 sport->rx_buf + rx_ring->tail, r_bytes);
1247
1248 /* UART retrieves ownership of RX DMA buffer */
1249 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1250 DMA_FROM_DEVICE);
1251
1252 if (w_bytes != r_bytes)
1253 sport->port.icount.buf_overrun++;
1254
1255 sport->port.icount.rx += w_bytes;
1256 }
1257 } else {
1258 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1259 WARN_ON(rx_ring->head <= rx_ring->tail);
1260 }
1261
1262 if (w_bytes) {
1263 tty_flip_buffer_push(port);
1264 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1265 }
1266 }
1267
imx_uart_start_rx_dma(struct imx_port * sport)1268 static int imx_uart_start_rx_dma(struct imx_port *sport)
1269 {
1270 struct scatterlist *sgl = &sport->rx_sgl;
1271 struct dma_chan *chan = sport->dma_chan_rx;
1272 struct device *dev = sport->port.dev;
1273 struct dma_async_tx_descriptor *desc;
1274 int ret;
1275
1276 sport->rx_ring.head = 0;
1277 sport->rx_ring.tail = 0;
1278
1279 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size);
1280 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1281 if (ret == 0) {
1282 dev_err(dev, "DMA mapping error for RX.\n");
1283 return -EINVAL;
1284 }
1285
1286 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1287 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1288 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1289
1290 if (!desc) {
1291 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1292 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1293 return -EINVAL;
1294 }
1295 desc->callback = imx_uart_dma_rx_callback;
1296 desc->callback_param = sport;
1297
1298 dev_dbg(dev, "RX: prepare for the DMA.\n");
1299 sport->dma_is_rxing = 1;
1300 sport->rx_cookie = dmaengine_submit(desc);
1301 dma_async_issue_pending(chan);
1302 return 0;
1303 }
1304
imx_uart_clear_rx_errors(struct imx_port * sport)1305 static void imx_uart_clear_rx_errors(struct imx_port *sport)
1306 {
1307 struct tty_port *port = &sport->port.state->port;
1308 u32 usr1, usr2;
1309
1310 usr1 = imx_uart_readl(sport, USR1);
1311 usr2 = imx_uart_readl(sport, USR2);
1312
1313 if (usr2 & USR2_BRCD) {
1314 sport->port.icount.brk++;
1315 imx_uart_writel(sport, USR2_BRCD, USR2);
1316 uart_handle_break(&sport->port);
1317 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1318 sport->port.icount.buf_overrun++;
1319 tty_flip_buffer_push(port);
1320 } else {
1321 if (usr1 & USR1_FRAMERR) {
1322 sport->port.icount.frame++;
1323 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1324 } else if (usr1 & USR1_PARITYERR) {
1325 sport->port.icount.parity++;
1326 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1327 }
1328 }
1329
1330 if (usr2 & USR2_ORE) {
1331 sport->port.icount.overrun++;
1332 imx_uart_writel(sport, USR2_ORE, USR2);
1333 }
1334
1335 sport->idle_counter = 0;
1336
1337 }
1338
1339 #define TXTL_DEFAULT 8
1340 #define RXTL_DEFAULT 8 /* 8 characters or aging timer */
1341 #define RXTL_CONSOLE_DEFAULT 1
1342 #define TXTL_DMA 8 /* DMA burst setting */
1343 #define RXTL_DMA 9 /* DMA burst setting */
1344
imx_uart_setup_ufcr(struct imx_port * sport,unsigned char txwl,unsigned char rxwl)1345 static void imx_uart_setup_ufcr(struct imx_port *sport,
1346 unsigned char txwl, unsigned char rxwl)
1347 {
1348 unsigned int val;
1349
1350 /* set receiver / transmitter trigger level */
1351 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1352 val |= txwl << UFCR_TXTL_SHF | rxwl;
1353 imx_uart_writel(sport, val, UFCR);
1354 }
1355
imx_uart_dma_exit(struct imx_port * sport)1356 static void imx_uart_dma_exit(struct imx_port *sport)
1357 {
1358 if (sport->dma_chan_rx) {
1359 dmaengine_terminate_sync(sport->dma_chan_rx);
1360 dma_release_channel(sport->dma_chan_rx);
1361 sport->dma_chan_rx = NULL;
1362 sport->rx_cookie = -EINVAL;
1363 kfree(sport->rx_buf);
1364 sport->rx_buf = NULL;
1365 }
1366
1367 if (sport->dma_chan_tx) {
1368 dmaengine_terminate_sync(sport->dma_chan_tx);
1369 dma_release_channel(sport->dma_chan_tx);
1370 sport->dma_chan_tx = NULL;
1371 }
1372 }
1373
imx_uart_dma_init(struct imx_port * sport)1374 static int imx_uart_dma_init(struct imx_port *sport)
1375 {
1376 struct dma_slave_config slave_config = {};
1377 struct device *dev = sport->port.dev;
1378 int ret;
1379
1380 /* Prepare for RX : */
1381 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1382 if (!sport->dma_chan_rx) {
1383 dev_dbg(dev, "cannot get the DMA channel.\n");
1384 ret = -EINVAL;
1385 goto err;
1386 }
1387
1388 slave_config.direction = DMA_DEV_TO_MEM;
1389 slave_config.src_addr = sport->port.mapbase + URXD0;
1390 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1391 /* one byte less than the watermark level to enable the aging timer */
1392 slave_config.src_maxburst = RXTL_DMA - 1;
1393 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1394 if (ret) {
1395 dev_err(dev, "error in RX dma configuration.\n");
1396 goto err;
1397 }
1398
1399 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods;
1400 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL);
1401 if (!sport->rx_buf) {
1402 ret = -ENOMEM;
1403 goto err;
1404 }
1405 sport->rx_ring.buf = sport->rx_buf;
1406
1407 /* Prepare for TX : */
1408 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1409 if (!sport->dma_chan_tx) {
1410 dev_err(dev, "cannot get the TX DMA channel!\n");
1411 ret = -EINVAL;
1412 goto err;
1413 }
1414
1415 slave_config.direction = DMA_MEM_TO_DEV;
1416 slave_config.dst_addr = sport->port.mapbase + URTX0;
1417 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1418 slave_config.dst_maxburst = TXTL_DMA;
1419 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1420 if (ret) {
1421 dev_err(dev, "error in TX dma configuration.");
1422 goto err;
1423 }
1424
1425 return 0;
1426 err:
1427 imx_uart_dma_exit(sport);
1428 return ret;
1429 }
1430
imx_uart_enable_dma(struct imx_port * sport)1431 static void imx_uart_enable_dma(struct imx_port *sport)
1432 {
1433 u32 ucr1;
1434
1435 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1436
1437 /* set UCR1 */
1438 ucr1 = imx_uart_readl(sport, UCR1);
1439 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1440 imx_uart_writel(sport, ucr1, UCR1);
1441
1442 sport->dma_is_enabled = 1;
1443 }
1444
imx_uart_disable_dma(struct imx_port * sport)1445 static void imx_uart_disable_dma(struct imx_port *sport)
1446 {
1447 u32 ucr1;
1448
1449 /* clear UCR1 */
1450 ucr1 = imx_uart_readl(sport, UCR1);
1451 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1452 imx_uart_writel(sport, ucr1, UCR1);
1453
1454 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl);
1455
1456 sport->dma_is_enabled = 0;
1457 }
1458
1459 /* half the RX buffer size */
1460 #define CTSTL 16
1461
imx_uart_startup(struct uart_port * port)1462 static int imx_uart_startup(struct uart_port *port)
1463 {
1464 struct imx_port *sport = (struct imx_port *)port;
1465 int retval;
1466 unsigned long flags;
1467 int dma_is_inited = 0;
1468 u32 ucr1, ucr2, ucr3, ucr4;
1469
1470 retval = clk_prepare_enable(sport->clk_per);
1471 if (retval)
1472 return retval;
1473 retval = clk_prepare_enable(sport->clk_ipg);
1474 if (retval) {
1475 clk_disable_unprepare(sport->clk_per);
1476 return retval;
1477 }
1478
1479 if (uart_console(&sport->port))
1480 sport->rxtl = RXTL_CONSOLE_DEFAULT;
1481 else
1482 sport->rxtl = RXTL_DEFAULT;
1483
1484 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl);
1485
1486 /* disable the DREN bit (Data Ready interrupt enable) before
1487 * requesting IRQs
1488 */
1489 ucr4 = imx_uart_readl(sport, UCR4);
1490
1491 /* set the trigger level for CTS */
1492 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1493 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1494
1495 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1496
1497 /* Can we enable the DMA support? */
1498 if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
1499 dma_is_inited = 1;
1500
1501 spin_lock_irqsave(&sport->port.lock, flags);
1502
1503 /* Reset fifo's and state machines */
1504 imx_uart_soft_reset(sport);
1505
1506 /*
1507 * Finally, clear and enable interrupts
1508 */
1509 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1510 imx_uart_writel(sport, USR2_ORE, USR2);
1511
1512 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1513 ucr1 |= UCR1_UARTEN;
1514 if (sport->have_rtscts)
1515 ucr1 |= UCR1_RTSDEN;
1516
1517 imx_uart_writel(sport, ucr1, UCR1);
1518
1519 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1520 if (!dma_is_inited)
1521 ucr4 |= UCR4_OREN;
1522 if (sport->inverted_rx)
1523 ucr4 |= UCR4_INVR;
1524 imx_uart_writel(sport, ucr4, UCR4);
1525
1526 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1527 /*
1528 * configure tx polarity before enabling tx
1529 */
1530 if (sport->inverted_tx)
1531 ucr3 |= UCR3_INVT;
1532
1533 if (!imx_uart_is_imx1(sport)) {
1534 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1535
1536 if (sport->dte_mode)
1537 /* disable broken interrupts */
1538 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1539 }
1540 imx_uart_writel(sport, ucr3, UCR3);
1541
1542 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1543 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1544 if (!sport->have_rtscts)
1545 ucr2 |= UCR2_IRTS;
1546 /*
1547 * make sure the edge sensitive RTS-irq is disabled,
1548 * we're using RTSD instead.
1549 */
1550 if (!imx_uart_is_imx1(sport))
1551 ucr2 &= ~UCR2_RTSEN;
1552 imx_uart_writel(sport, ucr2, UCR2);
1553
1554 /*
1555 * Enable modem status interrupts
1556 */
1557 imx_uart_enable_ms(&sport->port);
1558
1559 if (dma_is_inited) {
1560 imx_uart_enable_dma(sport);
1561 imx_uart_start_rx_dma(sport);
1562 } else {
1563 ucr1 = imx_uart_readl(sport, UCR1);
1564 ucr1 |= UCR1_RRDYEN;
1565 imx_uart_writel(sport, ucr1, UCR1);
1566
1567 ucr2 = imx_uart_readl(sport, UCR2);
1568 ucr2 |= UCR2_ATEN;
1569 imx_uart_writel(sport, ucr2, UCR2);
1570 }
1571
1572 imx_uart_disable_loopback_rs485(sport);
1573
1574 spin_unlock_irqrestore(&sport->port.lock, flags);
1575
1576 return 0;
1577 }
1578
imx_uart_shutdown(struct uart_port * port)1579 static void imx_uart_shutdown(struct uart_port *port)
1580 {
1581 struct imx_port *sport = (struct imx_port *)port;
1582 unsigned long flags;
1583 u32 ucr1, ucr2, ucr4, uts;
1584
1585 if (sport->dma_is_enabled) {
1586 dmaengine_terminate_sync(sport->dma_chan_tx);
1587 if (sport->dma_is_txing) {
1588 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1589 sport->dma_tx_nents, DMA_TO_DEVICE);
1590 sport->dma_is_txing = 0;
1591 }
1592 dmaengine_terminate_sync(sport->dma_chan_rx);
1593 if (sport->dma_is_rxing) {
1594 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1595 1, DMA_FROM_DEVICE);
1596 sport->dma_is_rxing = 0;
1597 }
1598
1599 spin_lock_irqsave(&sport->port.lock, flags);
1600 imx_uart_stop_tx(port);
1601 imx_uart_stop_rx(port);
1602 imx_uart_disable_dma(sport);
1603 spin_unlock_irqrestore(&sport->port.lock, flags);
1604 imx_uart_dma_exit(sport);
1605 }
1606
1607 mctrl_gpio_disable_ms_sync(sport->gpios);
1608
1609 spin_lock_irqsave(&sport->port.lock, flags);
1610 ucr2 = imx_uart_readl(sport, UCR2);
1611 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1612 imx_uart_writel(sport, ucr2, UCR2);
1613 spin_unlock_irqrestore(&sport->port.lock, flags);
1614
1615 /*
1616 * Stop our timer.
1617 */
1618 del_timer_sync(&sport->timer);
1619
1620 /*
1621 * Disable all interrupts, port and break condition.
1622 */
1623
1624 spin_lock_irqsave(&sport->port.lock, flags);
1625
1626 ucr1 = imx_uart_readl(sport, UCR1);
1627 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN |
1628 UCR1_ATDMAEN | UCR1_SNDBRK);
1629 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
1630 if (port->rs485.flags & SER_RS485_ENABLED &&
1631 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
1632 sport->have_rtscts && !sport->have_rtsgpio) {
1633 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
1634 uts |= UTS_LOOP;
1635 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1636 ucr1 |= UCR1_UARTEN;
1637 } else {
1638 ucr1 &= ~UCR1_UARTEN;
1639 }
1640 imx_uart_writel(sport, ucr1, UCR1);
1641
1642 ucr4 = imx_uart_readl(sport, UCR4);
1643 ucr4 &= ~UCR4_TCEN;
1644 imx_uart_writel(sport, ucr4, UCR4);
1645
1646 spin_unlock_irqrestore(&sport->port.lock, flags);
1647
1648 clk_disable_unprepare(sport->clk_per);
1649 clk_disable_unprepare(sport->clk_ipg);
1650 }
1651
1652 /* called with port.lock taken and irqs off */
imx_uart_flush_buffer(struct uart_port * port)1653 static void imx_uart_flush_buffer(struct uart_port *port)
1654 {
1655 struct imx_port *sport = (struct imx_port *)port;
1656 struct scatterlist *sgl = &sport->tx_sgl[0];
1657
1658 if (!sport->dma_chan_tx)
1659 return;
1660
1661 sport->tx_bytes = 0;
1662 dmaengine_terminate_all(sport->dma_chan_tx);
1663 if (sport->dma_is_txing) {
1664 u32 ucr1;
1665
1666 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1667 DMA_TO_DEVICE);
1668 ucr1 = imx_uart_readl(sport, UCR1);
1669 ucr1 &= ~UCR1_TXDMAEN;
1670 imx_uart_writel(sport, ucr1, UCR1);
1671 sport->dma_is_txing = 0;
1672 }
1673
1674 imx_uart_soft_reset(sport);
1675
1676 }
1677
1678 static void
imx_uart_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)1679 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1680 const struct ktermios *old)
1681 {
1682 struct imx_port *sport = (struct imx_port *)port;
1683 unsigned long flags;
1684 u32 ucr2, old_ucr2, ufcr;
1685 unsigned int baud, quot;
1686 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1687 unsigned long div;
1688 unsigned long num, denom, old_ubir, old_ubmr;
1689 uint64_t tdiv64;
1690
1691 /*
1692 * We only support CS7 and CS8.
1693 */
1694 while ((termios->c_cflag & CSIZE) != CS7 &&
1695 (termios->c_cflag & CSIZE) != CS8) {
1696 termios->c_cflag &= ~CSIZE;
1697 termios->c_cflag |= old_csize;
1698 old_csize = CS8;
1699 }
1700
1701 del_timer_sync(&sport->timer);
1702
1703 /*
1704 * Ask the core to calculate the divisor for us.
1705 */
1706 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1707 quot = uart_get_divisor(port, baud);
1708
1709 spin_lock_irqsave(&sport->port.lock, flags);
1710
1711 /*
1712 * Read current UCR2 and save it for future use, then clear all the bits
1713 * except those we will or may need to preserve.
1714 */
1715 old_ucr2 = imx_uart_readl(sport, UCR2);
1716 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1717
1718 ucr2 |= UCR2_SRST | UCR2_IRTS;
1719 if ((termios->c_cflag & CSIZE) == CS8)
1720 ucr2 |= UCR2_WS;
1721
1722 if (!sport->have_rtscts)
1723 termios->c_cflag &= ~CRTSCTS;
1724
1725 if (port->rs485.flags & SER_RS485_ENABLED) {
1726 /*
1727 * RTS is mandatory for rs485 operation, so keep
1728 * it under manual control and keep transmitter
1729 * disabled.
1730 */
1731 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1732 imx_uart_rts_active(sport, &ucr2);
1733 else
1734 imx_uart_rts_inactive(sport, &ucr2);
1735
1736 } else if (termios->c_cflag & CRTSCTS) {
1737 /*
1738 * Only let receiver control RTS output if we were not requested
1739 * to have RTS inactive (which then should take precedence).
1740 */
1741 if (ucr2 & UCR2_CTS)
1742 ucr2 |= UCR2_CTSC;
1743 }
1744
1745 if (termios->c_cflag & CRTSCTS)
1746 ucr2 &= ~UCR2_IRTS;
1747 if (termios->c_cflag & CSTOPB)
1748 ucr2 |= UCR2_STPB;
1749 if (termios->c_cflag & PARENB) {
1750 ucr2 |= UCR2_PREN;
1751 if (termios->c_cflag & PARODD)
1752 ucr2 |= UCR2_PROE;
1753 }
1754
1755 sport->port.read_status_mask = 0;
1756 if (termios->c_iflag & INPCK)
1757 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1758 if (termios->c_iflag & (BRKINT | PARMRK))
1759 sport->port.read_status_mask |= URXD_BRK;
1760
1761 /*
1762 * Characters to ignore
1763 */
1764 sport->port.ignore_status_mask = 0;
1765 if (termios->c_iflag & IGNPAR)
1766 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1767 if (termios->c_iflag & IGNBRK) {
1768 sport->port.ignore_status_mask |= URXD_BRK;
1769 /*
1770 * If we're ignoring parity and break indicators,
1771 * ignore overruns too (for real raw support).
1772 */
1773 if (termios->c_iflag & IGNPAR)
1774 sport->port.ignore_status_mask |= URXD_OVRRUN;
1775 }
1776
1777 if ((termios->c_cflag & CREAD) == 0)
1778 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1779
1780 /*
1781 * Update the per-port timeout.
1782 */
1783 uart_update_timeout(port, termios->c_cflag, baud);
1784
1785 /* custom-baudrate handling */
1786 div = sport->port.uartclk / (baud * 16);
1787 if (baud == 38400 && quot != div)
1788 baud = sport->port.uartclk / (quot * 16);
1789
1790 div = sport->port.uartclk / (baud * 16);
1791 if (div > 7)
1792 div = 7;
1793 if (!div)
1794 div = 1;
1795
1796 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1797 1 << 16, 1 << 16, &num, &denom);
1798
1799 tdiv64 = sport->port.uartclk;
1800 tdiv64 *= num;
1801 do_div(tdiv64, denom * 16 * div);
1802 tty_termios_encode_baud_rate(termios,
1803 (speed_t)tdiv64, (speed_t)tdiv64);
1804
1805 num -= 1;
1806 denom -= 1;
1807
1808 ufcr = imx_uart_readl(sport, UFCR);
1809 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1810 imx_uart_writel(sport, ufcr, UFCR);
1811
1812 /*
1813 * Two registers below should always be written both and in this
1814 * particular order. One consequence is that we need to check if any of
1815 * them changes and then update both. We do need the check for change
1816 * as even writing the same values seem to "restart"
1817 * transmission/receiving logic in the hardware, that leads to data
1818 * breakage even when rate doesn't in fact change. E.g., user switches
1819 * RTS/CTS handshake and suddenly gets broken bytes.
1820 */
1821 old_ubir = imx_uart_readl(sport, UBIR);
1822 old_ubmr = imx_uart_readl(sport, UBMR);
1823 if (old_ubir != num || old_ubmr != denom) {
1824 imx_uart_writel(sport, num, UBIR);
1825 imx_uart_writel(sport, denom, UBMR);
1826 }
1827
1828 if (!imx_uart_is_imx1(sport))
1829 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1830 IMX21_ONEMS);
1831
1832 imx_uart_writel(sport, ucr2, UCR2);
1833
1834 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1835 imx_uart_enable_ms(&sport->port);
1836
1837 spin_unlock_irqrestore(&sport->port.lock, flags);
1838 }
1839
imx_uart_type(struct uart_port * port)1840 static const char *imx_uart_type(struct uart_port *port)
1841 {
1842 return port->type == PORT_IMX ? "IMX" : NULL;
1843 }
1844
1845 /*
1846 * Configure/autoconfigure the port.
1847 */
imx_uart_config_port(struct uart_port * port,int flags)1848 static void imx_uart_config_port(struct uart_port *port, int flags)
1849 {
1850 if (flags & UART_CONFIG_TYPE)
1851 port->type = PORT_IMX;
1852 }
1853
1854 /*
1855 * Verify the new serial_struct (for TIOCSSERIAL).
1856 * The only change we allow are to the flags and type, and
1857 * even then only between PORT_IMX and PORT_UNKNOWN
1858 */
1859 static int
imx_uart_verify_port(struct uart_port * port,struct serial_struct * ser)1860 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1861 {
1862 int ret = 0;
1863
1864 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1865 ret = -EINVAL;
1866 if (port->irq != ser->irq)
1867 ret = -EINVAL;
1868 if (ser->io_type != UPIO_MEM)
1869 ret = -EINVAL;
1870 if (port->uartclk / 16 != ser->baud_base)
1871 ret = -EINVAL;
1872 if (port->mapbase != (unsigned long)ser->iomem_base)
1873 ret = -EINVAL;
1874 if (port->iobase != ser->port)
1875 ret = -EINVAL;
1876 if (ser->hub6 != 0)
1877 ret = -EINVAL;
1878 return ret;
1879 }
1880
1881 #if defined(CONFIG_CONSOLE_POLL)
1882
imx_uart_poll_init(struct uart_port * port)1883 static int imx_uart_poll_init(struct uart_port *port)
1884 {
1885 struct imx_port *sport = (struct imx_port *)port;
1886 unsigned long flags;
1887 u32 ucr1, ucr2;
1888 int retval;
1889
1890 retval = clk_prepare_enable(sport->clk_ipg);
1891 if (retval)
1892 return retval;
1893 retval = clk_prepare_enable(sport->clk_per);
1894 if (retval)
1895 clk_disable_unprepare(sport->clk_ipg);
1896
1897 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl);
1898
1899 spin_lock_irqsave(&sport->port.lock, flags);
1900
1901 /*
1902 * Be careful about the order of enabling bits here. First enable the
1903 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1904 * This prevents that a character that already sits in the RX fifo is
1905 * triggering an irq but the try to fetch it from there results in an
1906 * exception because UARTEN or RXEN is still off.
1907 */
1908 ucr1 = imx_uart_readl(sport, UCR1);
1909 ucr2 = imx_uart_readl(sport, UCR2);
1910
1911 if (imx_uart_is_imx1(sport))
1912 ucr1 |= IMX1_UCR1_UARTCLKEN;
1913
1914 ucr1 |= UCR1_UARTEN;
1915 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1916
1917 ucr2 |= UCR2_RXEN | UCR2_TXEN;
1918 ucr2 &= ~UCR2_ATEN;
1919
1920 imx_uart_writel(sport, ucr1, UCR1);
1921 imx_uart_writel(sport, ucr2, UCR2);
1922
1923 /* now enable irqs */
1924 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1925 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1926
1927 spin_unlock_irqrestore(&sport->port.lock, flags);
1928
1929 return 0;
1930 }
1931
imx_uart_poll_get_char(struct uart_port * port)1932 static int imx_uart_poll_get_char(struct uart_port *port)
1933 {
1934 struct imx_port *sport = (struct imx_port *)port;
1935 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1936 return NO_POLL_CHAR;
1937
1938 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1939 }
1940
imx_uart_poll_put_char(struct uart_port * port,unsigned char c)1941 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1942 {
1943 struct imx_port *sport = (struct imx_port *)port;
1944 unsigned int status;
1945
1946 /* drain */
1947 do {
1948 status = imx_uart_readl(sport, USR1);
1949 } while (~status & USR1_TRDY);
1950
1951 /* write */
1952 imx_uart_writel(sport, c, URTX0);
1953
1954 /* flush */
1955 do {
1956 status = imx_uart_readl(sport, USR2);
1957 } while (~status & USR2_TXDC);
1958 }
1959 #endif
1960
1961 /* called with port.lock taken and irqs off or from .probe without locking */
imx_uart_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485conf)1962 static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termios,
1963 struct serial_rs485 *rs485conf)
1964 {
1965 struct imx_port *sport = (struct imx_port *)port;
1966 u32 ucr2, ufcr;
1967
1968 if (rs485conf->flags & SER_RS485_ENABLED) {
1969 /* Enable receiver if low-active RTS signal is requested */
1970 if (sport->have_rtscts && !sport->have_rtsgpio &&
1971 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1972 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1973
1974 /* disable transmitter */
1975 ucr2 = imx_uart_readl(sport, UCR2);
1976 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1977 imx_uart_rts_active(sport, &ucr2);
1978 else
1979 imx_uart_rts_inactive(sport, &ucr2);
1980 imx_uart_writel(sport, ucr2, UCR2);
1981 }
1982
1983 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1984 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1985 rs485conf->flags & SER_RS485_RX_DURING_TX) {
1986 /* If the receiver trigger is 0, set it to a default value */
1987 ufcr = imx_uart_readl(sport, UFCR);
1988 if ((ufcr & UFCR_RXTL_MASK) == 0)
1989 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl);
1990 imx_uart_start_rx(port);
1991 }
1992
1993 return 0;
1994 }
1995
1996 static const struct uart_ops imx_uart_pops = {
1997 .tx_empty = imx_uart_tx_empty,
1998 .set_mctrl = imx_uart_set_mctrl,
1999 .get_mctrl = imx_uart_get_mctrl,
2000 .stop_tx = imx_uart_stop_tx,
2001 .start_tx = imx_uart_start_tx,
2002 .stop_rx = imx_uart_stop_rx,
2003 .enable_ms = imx_uart_enable_ms,
2004 .break_ctl = imx_uart_break_ctl,
2005 .startup = imx_uart_startup,
2006 .shutdown = imx_uart_shutdown,
2007 .flush_buffer = imx_uart_flush_buffer,
2008 .set_termios = imx_uart_set_termios,
2009 .type = imx_uart_type,
2010 .config_port = imx_uart_config_port,
2011 .verify_port = imx_uart_verify_port,
2012 #if defined(CONFIG_CONSOLE_POLL)
2013 .poll_init = imx_uart_poll_init,
2014 .poll_get_char = imx_uart_poll_get_char,
2015 .poll_put_char = imx_uart_poll_put_char,
2016 #endif
2017 };
2018
2019 static struct imx_port *imx_uart_ports[UART_NR];
2020
2021 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_console_putchar(struct uart_port * port,unsigned char ch)2022 static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch)
2023 {
2024 struct imx_port *sport = (struct imx_port *)port;
2025
2026 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
2027 barrier();
2028
2029 imx_uart_writel(sport, ch, URTX0);
2030 }
2031
2032 /*
2033 * Interrupts are disabled on entering
2034 */
2035 static void
imx_uart_console_write(struct console * co,const char * s,unsigned int count)2036 imx_uart_console_write(struct console *co, const char *s, unsigned int count)
2037 {
2038 struct imx_port *sport = imx_uart_ports[co->index];
2039 struct imx_port_ucrs old_ucr;
2040 unsigned long flags;
2041 unsigned int ucr1, usr2;
2042 int locked = 1;
2043
2044 if (sport->port.sysrq)
2045 locked = 0;
2046 else if (oops_in_progress)
2047 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2048 else
2049 spin_lock_irqsave(&sport->port.lock, flags);
2050
2051 /*
2052 * First, save UCR1/2/3 and then disable interrupts
2053 */
2054 imx_uart_ucrs_save(sport, &old_ucr);
2055 ucr1 = old_ucr.ucr1;
2056
2057 if (imx_uart_is_imx1(sport))
2058 ucr1 |= IMX1_UCR1_UARTCLKEN;
2059 ucr1 |= UCR1_UARTEN;
2060 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2061
2062 imx_uart_writel(sport, ucr1, UCR1);
2063
2064 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2065
2066 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
2067
2068 /*
2069 * Finally, wait for transmitter to become empty
2070 * and restore UCR1/2/3
2071 */
2072 read_poll_timeout_atomic(imx_uart_readl, usr2, usr2 & USR2_TXDC,
2073 0, USEC_PER_SEC, false, sport, USR2);
2074 imx_uart_ucrs_restore(sport, &old_ucr);
2075
2076 if (locked)
2077 spin_unlock_irqrestore(&sport->port.lock, flags);
2078 }
2079
2080 /*
2081 * If the port was already initialised (eg, by a boot loader),
2082 * try to determine the current setup.
2083 */
2084 static void
imx_uart_console_get_options(struct imx_port * sport,int * baud,int * parity,int * bits)2085 imx_uart_console_get_options(struct imx_port *sport, int *baud,
2086 int *parity, int *bits)
2087 {
2088
2089 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2090 /* ok, the port was enabled */
2091 unsigned int ucr2, ubir, ubmr, uartclk;
2092 unsigned int baud_raw;
2093 unsigned int ucfr_rfdiv;
2094
2095 ucr2 = imx_uart_readl(sport, UCR2);
2096
2097 *parity = 'n';
2098 if (ucr2 & UCR2_PREN) {
2099 if (ucr2 & UCR2_PROE)
2100 *parity = 'o';
2101 else
2102 *parity = 'e';
2103 }
2104
2105 if (ucr2 & UCR2_WS)
2106 *bits = 8;
2107 else
2108 *bits = 7;
2109
2110 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2111 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2112
2113 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2114 if (ucfr_rfdiv == 6)
2115 ucfr_rfdiv = 7;
2116 else
2117 ucfr_rfdiv = 6 - ucfr_rfdiv;
2118
2119 uartclk = clk_get_rate(sport->clk_per);
2120 uartclk /= ucfr_rfdiv;
2121
2122 { /*
2123 * The next code provides exact computation of
2124 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2125 * without need of float support or long long division,
2126 * which would be required to prevent 32bit arithmetic overflow
2127 */
2128 unsigned int mul = ubir + 1;
2129 unsigned int div = 16 * (ubmr + 1);
2130 unsigned int rem = uartclk % div;
2131
2132 baud_raw = (uartclk / div) * mul;
2133 baud_raw += (rem * mul + div / 2) / div;
2134 *baud = (baud_raw + 50) / 100 * 100;
2135 }
2136
2137 if (*baud != baud_raw)
2138 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2139 baud_raw, *baud);
2140 }
2141 }
2142
2143 static int
imx_uart_console_setup(struct console * co,char * options)2144 imx_uart_console_setup(struct console *co, char *options)
2145 {
2146 struct imx_port *sport;
2147 int baud = 9600;
2148 int bits = 8;
2149 int parity = 'n';
2150 int flow = 'n';
2151 int retval;
2152
2153 /*
2154 * Check whether an invalid uart number has been specified, and
2155 * if so, search for the first available port that does have
2156 * console support.
2157 */
2158 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2159 co->index = 0;
2160 sport = imx_uart_ports[co->index];
2161 if (sport == NULL)
2162 return -ENODEV;
2163
2164 /* For setting the registers, we only need to enable the ipg clock. */
2165 retval = clk_prepare_enable(sport->clk_ipg);
2166 if (retval)
2167 goto error_console;
2168
2169 if (options)
2170 uart_parse_options(options, &baud, &parity, &bits, &flow);
2171 else
2172 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2173
2174 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl);
2175
2176 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2177
2178 if (retval) {
2179 clk_disable_unprepare(sport->clk_ipg);
2180 goto error_console;
2181 }
2182
2183 retval = clk_prepare_enable(sport->clk_per);
2184 if (retval)
2185 clk_disable_unprepare(sport->clk_ipg);
2186
2187 error_console:
2188 return retval;
2189 }
2190
2191 static int
imx_uart_console_exit(struct console * co)2192 imx_uart_console_exit(struct console *co)
2193 {
2194 struct imx_port *sport = imx_uart_ports[co->index];
2195
2196 clk_disable_unprepare(sport->clk_per);
2197 clk_disable_unprepare(sport->clk_ipg);
2198
2199 return 0;
2200 }
2201
2202 static struct uart_driver imx_uart_uart_driver;
2203 static struct console imx_uart_console = {
2204 .name = DEV_NAME,
2205 .write = imx_uart_console_write,
2206 .device = uart_console_device,
2207 .setup = imx_uart_console_setup,
2208 .exit = imx_uart_console_exit,
2209 .flags = CON_PRINTBUFFER,
2210 .index = -1,
2211 .data = &imx_uart_uart_driver,
2212 };
2213
2214 #define IMX_CONSOLE &imx_uart_console
2215
2216 #else
2217 #define IMX_CONSOLE NULL
2218 #endif
2219
2220 static struct uart_driver imx_uart_uart_driver = {
2221 .owner = THIS_MODULE,
2222 .driver_name = DRIVER_NAME,
2223 .dev_name = DEV_NAME,
2224 .major = SERIAL_IMX_MAJOR,
2225 .minor = MINOR_START,
2226 .nr = ARRAY_SIZE(imx_uart_ports),
2227 .cons = IMX_CONSOLE,
2228 };
2229
imx_trigger_start_tx(struct hrtimer * t)2230 static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2231 {
2232 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2233 unsigned long flags;
2234
2235 spin_lock_irqsave(&sport->port.lock, flags);
2236 if (sport->tx_state == WAIT_AFTER_RTS)
2237 imx_uart_start_tx(&sport->port);
2238 spin_unlock_irqrestore(&sport->port.lock, flags);
2239
2240 return HRTIMER_NORESTART;
2241 }
2242
imx_trigger_stop_tx(struct hrtimer * t)2243 static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2244 {
2245 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2246 unsigned long flags;
2247
2248 spin_lock_irqsave(&sport->port.lock, flags);
2249 if (sport->tx_state == WAIT_AFTER_SEND)
2250 imx_uart_stop_tx(&sport->port);
2251 spin_unlock_irqrestore(&sport->port.lock, flags);
2252
2253 return HRTIMER_NORESTART;
2254 }
2255
2256 static const struct serial_rs485 imx_rs485_supported = {
2257 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
2258 SER_RS485_RX_DURING_TX,
2259 .delay_rts_before_send = 1,
2260 .delay_rts_after_send = 1,
2261 };
2262
2263 /* Default RX DMA buffer configuration */
2264 #define RX_DMA_PERIODS 16
2265 #define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4)
2266
imx_uart_probe(struct platform_device * pdev)2267 static int imx_uart_probe(struct platform_device *pdev)
2268 {
2269 struct device_node *np = pdev->dev.of_node;
2270 struct imx_port *sport;
2271 void __iomem *base;
2272 u32 dma_buf_conf[2];
2273 int ret = 0;
2274 u32 ucr1, ucr2, uts;
2275 struct resource *res;
2276 int txirq, rxirq, rtsirq;
2277
2278 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2279 if (!sport)
2280 return -ENOMEM;
2281
2282 sport->devdata = of_device_get_match_data(&pdev->dev);
2283
2284 ret = of_alias_get_id(np, "serial");
2285 if (ret < 0) {
2286 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2287 return ret;
2288 }
2289 sport->port.line = ret;
2290
2291 sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") ||
2292 of_property_read_bool(np, "fsl,uart-has-rtscts"); /* deprecated */
2293
2294 sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode");
2295
2296 sport->have_rtsgpio = of_property_present(np, "rts-gpios");
2297
2298 sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx");
2299
2300 sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx");
2301
2302 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) {
2303 sport->rx_period_length = dma_buf_conf[0];
2304 sport->rx_periods = dma_buf_conf[1];
2305 } else {
2306 sport->rx_period_length = RX_DMA_PERIOD_LEN;
2307 sport->rx_periods = RX_DMA_PERIODS;
2308 }
2309
2310 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2311 dev_err(&pdev->dev, "serial%d out of range\n",
2312 sport->port.line);
2313 return -EINVAL;
2314 }
2315
2316 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2317 if (IS_ERR(base))
2318 return PTR_ERR(base);
2319
2320 rxirq = platform_get_irq(pdev, 0);
2321 if (rxirq < 0)
2322 return rxirq;
2323 txirq = platform_get_irq_optional(pdev, 1);
2324 rtsirq = platform_get_irq_optional(pdev, 2);
2325
2326 sport->port.dev = &pdev->dev;
2327 sport->port.mapbase = res->start;
2328 sport->port.membase = base;
2329 sport->port.type = PORT_IMX;
2330 sport->port.iotype = UPIO_MEM;
2331 sport->port.irq = rxirq;
2332 sport->port.fifosize = 32;
2333 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2334 sport->port.ops = &imx_uart_pops;
2335 sport->port.rs485_config = imx_uart_rs485_config;
2336 /* RTS is required to control the RS485 transmitter */
2337 if (sport->have_rtscts || sport->have_rtsgpio)
2338 sport->port.rs485_supported = imx_rs485_supported;
2339 sport->port.flags = UPF_BOOT_AUTOCONF;
2340 timer_setup(&sport->timer, imx_uart_timeout, 0);
2341
2342 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2343 if (IS_ERR(sport->gpios))
2344 return PTR_ERR(sport->gpios);
2345
2346 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2347 if (IS_ERR(sport->clk_ipg)) {
2348 ret = PTR_ERR(sport->clk_ipg);
2349 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2350 return ret;
2351 }
2352
2353 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2354 if (IS_ERR(sport->clk_per)) {
2355 ret = PTR_ERR(sport->clk_per);
2356 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2357 return ret;
2358 }
2359
2360 sport->port.uartclk = clk_get_rate(sport->clk_per);
2361
2362 /* For register access, we only need to enable the ipg clock. */
2363 ret = clk_prepare_enable(sport->clk_ipg);
2364 if (ret) {
2365 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
2366 return ret;
2367 }
2368
2369 ret = uart_get_rs485_mode(&sport->port);
2370 if (ret)
2371 goto err_clk;
2372
2373 /*
2374 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2375 * signal cannot be set low during transmission in case the
2376 * receiver is off (limitation of the i.MX UART IP).
2377 */
2378 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2379 sport->have_rtscts && !sport->have_rtsgpio &&
2380 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2381 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2382 dev_err(&pdev->dev,
2383 "low-active RTS not possible when receiver is off, enabling receiver\n");
2384
2385 /* Disable interrupts before requesting them */
2386 ucr1 = imx_uart_readl(sport, UCR1);
2387 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
2388 imx_uart_writel(sport, ucr1, UCR1);
2389
2390 /* Disable Ageing Timer interrupt */
2391 ucr2 = imx_uart_readl(sport, UCR2);
2392 ucr2 &= ~UCR2_ATEN;
2393 imx_uart_writel(sport, ucr2, UCR2);
2394
2395 /*
2396 * In case RS485 is enabled without GPIO RTS control, the UART IP
2397 * is used to control CTS signal. Keep both the UART and Receiver
2398 * enabled, otherwise the UART IP pulls CTS signal always HIGH no
2399 * matter how the UCR2 CTSC and CTS bits are set. To prevent any
2400 * data from being fed into the RX FIFO, enable loopback mode in
2401 * UTS register, which disconnects the RX path from external RXD
2402 * pin and connects it to the Transceiver, which is disabled, so
2403 * no data can be fed to the RX FIFO that way.
2404 */
2405 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2406 sport->have_rtscts && !sport->have_rtsgpio) {
2407 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
2408 uts |= UTS_LOOP;
2409 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
2410
2411 ucr1 = imx_uart_readl(sport, UCR1);
2412 ucr1 |= UCR1_UARTEN;
2413 imx_uart_writel(sport, ucr1, UCR1);
2414
2415 ucr2 = imx_uart_readl(sport, UCR2);
2416 ucr2 |= UCR2_RXEN;
2417 imx_uart_writel(sport, ucr2, UCR2);
2418 }
2419
2420 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2421 /*
2422 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2423 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2424 * and DCD (when they are outputs) or enables the respective
2425 * irqs. So set this bit early, i.e. before requesting irqs.
2426 */
2427 u32 ufcr = imx_uart_readl(sport, UFCR);
2428 if (!(ufcr & UFCR_DCEDTE))
2429 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2430
2431 /*
2432 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2433 * enabled later because they cannot be cleared
2434 * (confirmed on i.MX25) which makes them unusable.
2435 */
2436 imx_uart_writel(sport,
2437 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2438 UCR3);
2439
2440 } else {
2441 u32 ucr3 = UCR3_DSR;
2442 u32 ufcr = imx_uart_readl(sport, UFCR);
2443 if (ufcr & UFCR_DCEDTE)
2444 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2445
2446 if (!imx_uart_is_imx1(sport))
2447 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2448 imx_uart_writel(sport, ucr3, UCR3);
2449 }
2450
2451 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2452 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2453 sport->trigger_start_tx.function = imx_trigger_start_tx;
2454 sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2455
2456 /*
2457 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2458 * chips only have one interrupt.
2459 */
2460 if (txirq > 0) {
2461 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2462 dev_name(&pdev->dev), sport);
2463 if (ret) {
2464 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2465 ret);
2466 goto err_clk;
2467 }
2468
2469 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2470 dev_name(&pdev->dev), sport);
2471 if (ret) {
2472 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2473 ret);
2474 goto err_clk;
2475 }
2476
2477 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2478 dev_name(&pdev->dev), sport);
2479 if (ret) {
2480 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2481 ret);
2482 goto err_clk;
2483 }
2484 } else {
2485 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2486 dev_name(&pdev->dev), sport);
2487 if (ret) {
2488 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2489 goto err_clk;
2490 }
2491 }
2492
2493 imx_uart_ports[sport->port.line] = sport;
2494
2495 platform_set_drvdata(pdev, sport);
2496
2497 ret = uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2498
2499 err_clk:
2500 clk_disable_unprepare(sport->clk_ipg);
2501
2502 return ret;
2503 }
2504
imx_uart_remove(struct platform_device * pdev)2505 static int imx_uart_remove(struct platform_device *pdev)
2506 {
2507 struct imx_port *sport = platform_get_drvdata(pdev);
2508
2509 uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2510
2511 return 0;
2512 }
2513
imx_uart_restore_context(struct imx_port * sport)2514 static void imx_uart_restore_context(struct imx_port *sport)
2515 {
2516 unsigned long flags;
2517
2518 spin_lock_irqsave(&sport->port.lock, flags);
2519 if (!sport->context_saved) {
2520 spin_unlock_irqrestore(&sport->port.lock, flags);
2521 return;
2522 }
2523
2524 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2525 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2526 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2527 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2528 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2529 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2530 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2531 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2532 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2533 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2534 sport->context_saved = false;
2535 spin_unlock_irqrestore(&sport->port.lock, flags);
2536 }
2537
imx_uart_save_context(struct imx_port * sport)2538 static void imx_uart_save_context(struct imx_port *sport)
2539 {
2540 unsigned long flags;
2541
2542 /* Save necessary regs */
2543 spin_lock_irqsave(&sport->port.lock, flags);
2544 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2545 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2546 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2547 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2548 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2549 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2550 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2551 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2552 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2553 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2554 sport->context_saved = true;
2555 spin_unlock_irqrestore(&sport->port.lock, flags);
2556 }
2557
imx_uart_enable_wakeup(struct imx_port * sport,bool on)2558 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2559 {
2560 u32 ucr3;
2561
2562 ucr3 = imx_uart_readl(sport, UCR3);
2563 if (on) {
2564 imx_uart_writel(sport, USR1_AWAKE, USR1);
2565 ucr3 |= UCR3_AWAKEN;
2566 } else {
2567 ucr3 &= ~UCR3_AWAKEN;
2568 }
2569 imx_uart_writel(sport, ucr3, UCR3);
2570
2571 if (sport->have_rtscts) {
2572 u32 ucr1 = imx_uart_readl(sport, UCR1);
2573 if (on) {
2574 imx_uart_writel(sport, USR1_RTSD, USR1);
2575 ucr1 |= UCR1_RTSDEN;
2576 } else {
2577 ucr1 &= ~UCR1_RTSDEN;
2578 }
2579 imx_uart_writel(sport, ucr1, UCR1);
2580 }
2581 }
2582
imx_uart_suspend_noirq(struct device * dev)2583 static int imx_uart_suspend_noirq(struct device *dev)
2584 {
2585 struct imx_port *sport = dev_get_drvdata(dev);
2586
2587 imx_uart_save_context(sport);
2588
2589 clk_disable(sport->clk_ipg);
2590
2591 pinctrl_pm_select_sleep_state(dev);
2592
2593 return 0;
2594 }
2595
imx_uart_resume_noirq(struct device * dev)2596 static int imx_uart_resume_noirq(struct device *dev)
2597 {
2598 struct imx_port *sport = dev_get_drvdata(dev);
2599 int ret;
2600
2601 pinctrl_pm_select_default_state(dev);
2602
2603 ret = clk_enable(sport->clk_ipg);
2604 if (ret)
2605 return ret;
2606
2607 imx_uart_restore_context(sport);
2608
2609 return 0;
2610 }
2611
imx_uart_suspend(struct device * dev)2612 static int imx_uart_suspend(struct device *dev)
2613 {
2614 struct imx_port *sport = dev_get_drvdata(dev);
2615 int ret;
2616
2617 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2618 disable_irq(sport->port.irq);
2619
2620 ret = clk_prepare_enable(sport->clk_ipg);
2621 if (ret)
2622 return ret;
2623
2624 /* enable wakeup from i.MX UART */
2625 imx_uart_enable_wakeup(sport, true);
2626
2627 return 0;
2628 }
2629
imx_uart_resume(struct device * dev)2630 static int imx_uart_resume(struct device *dev)
2631 {
2632 struct imx_port *sport = dev_get_drvdata(dev);
2633
2634 /* disable wakeup from i.MX UART */
2635 imx_uart_enable_wakeup(sport, false);
2636
2637 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2638 enable_irq(sport->port.irq);
2639
2640 clk_disable_unprepare(sport->clk_ipg);
2641
2642 return 0;
2643 }
2644
imx_uart_freeze(struct device * dev)2645 static int imx_uart_freeze(struct device *dev)
2646 {
2647 struct imx_port *sport = dev_get_drvdata(dev);
2648
2649 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2650
2651 return clk_prepare_enable(sport->clk_ipg);
2652 }
2653
imx_uart_thaw(struct device * dev)2654 static int imx_uart_thaw(struct device *dev)
2655 {
2656 struct imx_port *sport = dev_get_drvdata(dev);
2657
2658 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2659
2660 clk_disable_unprepare(sport->clk_ipg);
2661
2662 return 0;
2663 }
2664
2665 static const struct dev_pm_ops imx_uart_pm_ops = {
2666 .suspend_noirq = imx_uart_suspend_noirq,
2667 .resume_noirq = imx_uart_resume_noirq,
2668 .freeze_noirq = imx_uart_suspend_noirq,
2669 .thaw_noirq = imx_uart_resume_noirq,
2670 .restore_noirq = imx_uart_resume_noirq,
2671 .suspend = imx_uart_suspend,
2672 .resume = imx_uart_resume,
2673 .freeze = imx_uart_freeze,
2674 .thaw = imx_uart_thaw,
2675 .restore = imx_uart_thaw,
2676 };
2677
2678 static struct platform_driver imx_uart_platform_driver = {
2679 .probe = imx_uart_probe,
2680 .remove = imx_uart_remove,
2681
2682 .driver = {
2683 .name = "imx-uart",
2684 .of_match_table = imx_uart_dt_ids,
2685 .pm = &imx_uart_pm_ops,
2686 },
2687 };
2688
imx_uart_init(void)2689 static int __init imx_uart_init(void)
2690 {
2691 int ret = uart_register_driver(&imx_uart_uart_driver);
2692
2693 if (ret)
2694 return ret;
2695
2696 ret = platform_driver_register(&imx_uart_platform_driver);
2697 if (ret != 0)
2698 uart_unregister_driver(&imx_uart_uart_driver);
2699
2700 return ret;
2701 }
2702
imx_uart_exit(void)2703 static void __exit imx_uart_exit(void)
2704 {
2705 platform_driver_unregister(&imx_uart_platform_driver);
2706 uart_unregister_driver(&imx_uart_uart_driver);
2707 }
2708
2709 module_init(imx_uart_init);
2710 module_exit(imx_uart_exit);
2711
2712 MODULE_AUTHOR("Sascha Hauer");
2713 MODULE_DESCRIPTION("IMX generic serial port driver");
2714 MODULE_LICENSE("GPL");
2715 MODULE_ALIAS("platform:imx-uart");
2716