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Searched defs:I2C1_BASE_ADDR (Results 1 – 15 of 15) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-stv0991/
H A Dhardware.h50 #define I2C1_BASE_ADDR 0x80401000UL macro
/openbmc/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dconfig.h52 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) macro
/openbmc/u-boot/arch/arm/include/asm/arch-mx35/
H A Dimx-regs.h29 #define I2C1_BASE_ADDR 0x43F80000 macro
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dimx-regs.h87 #define I2C1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000038000) macro
/openbmc/u-boot/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h186 #define I2C1_BASE_ADDR (0x12000 + IMX_IO_BASE) macro
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dimmap_lsch3.h50 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) macro
H A Dimmap_lsch2.h73 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) macro
/openbmc/u-boot/arch/arm/include/asm/arch-imx/
H A Dimx-regs.h45 #define I2C1_BASE_ADDR (0x17000 + IMX_IO_BASE) macro
/openbmc/u-boot/arch/arm/include/asm/arch-mx5/
H A Dimx-regs.h109 #define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) macro
/openbmc/u-boot/arch/arm/include/asm/arch-vf610/
H A Dimx-regs.h77 #define I2C1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000) macro
/openbmc/u-boot/arch/arm/include/asm/arch-mx25/
H A Dimx-regs.h295 #define I2C1_BASE_ADDR (0x43F80000) macro
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dimx-regs.h81 #define I2C1_BASE_ADDR 0x30A20000 macro
/openbmc/u-boot/arch/arm/include/asm/arch-mx31/
H A Dimx-regs.h612 #define I2C1_BASE_ADDR 0x43f80000 macro
/openbmc/u-boot/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h263 #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) macro
/openbmc/u-boot/arch/arm/include/asm/arch-mx7/
H A Dimx-regs.h173 #define I2C1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x20000) macro