| /openbmc/qemu/target/riscv/ |
| H A D | cpu.h | 197 struct CPUArchState { struct
198 target_ulong gpr[32];
199 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
202 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
203 target_ulong vxrm;
204 target_ulong vxsat;
205 target_ulong vl;
206 target_ulong vstart;
207 target_ulong vtype;
208 bool vill;
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| /openbmc/qemu/target/rx/ |
| H A D | cpu.h | 69 typedef struct CPUArchState { struct
71 uint32_t regs[NUM_REGS]; /* general registers */
72 uint32_t psw_o; /* O bit of status register */
73 uint32_t psw_s; /* S bit of status register */
74 uint32_t psw_z; /* Z bit of status register */
75 uint32_t psw_c; /* C bit of status register */
76 uint32_t psw_u;
77 uint32_t psw_i;
78 uint32_t psw_pm;
79 uint32_t psw_ipl;
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| /openbmc/qemu/target/loongarch/ |
| H A D | cpu.h | 301 typedef struct CPUArchState { struct
302 uint64_t gpr[32];
303 uint64_t pc;
305 fpr_t fpr[32];
306 bool cf[8];
307 uint32_t fcsr0;
308 lbt_t lbt;
310 uint32_t cpucfg[21];
313 uint64_t CSR_CRMD;
314 uint64_t CSR_PRMD;
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| /openbmc/qemu/target/hexagon/ |
| H A D | cpu.h | 71 typedef struct CPUArchState { struct
72 target_ulong gpr[TOTAL_PER_THREAD_REGS];
73 target_ulong pred[NUM_PREGS];
76 target_ulong last_pc_dumped;
77 target_ulong stack_start;
79 uint8_t slot_cancelled;
80 target_ulong new_value_usr;
86 target_ulong reg_written[TOTAL_PER_THREAD_REGS];
88 MemLog mem_log_stores[STORES_MAX];
90 float_status fp_status;
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| /openbmc/qemu/target/sparc/ |
| H A D | cpu.h | 402 struct CPUArchState { struct
403 target_ulong gregs[8]; /* general registers */
404 target_ulong *regwptr; /* pointer to current register window */
405 target_ulong pc; /* program counter */
406 target_ulong npc; /* next program counter */
407 target_ulong y; /* multiply/divide register */
413 target_long cc_N;
414 target_long cc_V;
420 target_ulong icc_Z;
422 target_ulong xcc_Z;
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| /openbmc/qemu/target/avr/ |
| H A D | cpu.h | 107 typedef struct CPUArchState { struct
108 uint32_t pc_w; /* 0x003fffff up to 22 bits */
110 uint32_t sregC; /* 0x00000001 1 bit */
111 uint32_t sregZ; /* 0x00000001 1 bit */
112 uint32_t sregN; /* 0x00000001 1 bit */
113 uint32_t sregV; /* 0x00000001 1 bit */
114 uint32_t sregS; /* 0x00000001 1 bit */
115 uint32_t sregH; /* 0x00000001 1 bit */
116 uint32_t sregT; /* 0x00000001 1 bit */
117 uint32_t sregI; /* 0x00000001 1 bit */
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| /openbmc/qemu/target/sh4/ |
| H A D | cpu.h | 141 typedef struct CPUArchState { struct
142 uint32_t flags; /* general execution flags */
143 uint32_t gregs[24]; /* general registers */
144 float32 fregs[32]; /* floating point registers */
145 uint32_t sr; /* status register (with T split out) */
146 uint32_t sr_m; /* M bit of status register */
147 uint32_t sr_q; /* Q bit of status register */
148 uint32_t sr_t; /* T bit of status register */
149 uint32_t ssr; /* saved status register */
150 uint32_t spc; /* saved program counter */
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| /openbmc/qemu/target/openrisc/ |
| H A D | cpu.h | 235 typedef struct CPUArchState { struct
236 target_ulong shadow_gpr[16][32]; /* Shadow registers */
238 target_ulong pc; /* Program counter */
239 target_ulong ppc; /* Prev PC */
240 target_ulong jmp_pc; /* Jump PC */
242 uint64_t mac; /* Multiply registers MACHI:MACLO */
244 target_ulong epcr; /* Exception PC register */
245 target_ulong eear; /* Exception EA register */
247 target_ulong sr_f; /* the SR_F bit, values 0, 1. */
248 target_ulong sr_cy; /* the SR_CY bit, values 0, 1. */
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| /openbmc/qemu/target/i386/ |
| H A D | cpu.h | 1736 typedef struct CPUArchState { struct
1738 target_ulong regs[CPU_NB_REGS];
1739 target_ulong eip;
1740 target_ulong eflags; /* eflags register. During CPU emulation, CC
1745 target_ulong cc_dst;
1746 target_ulong cc_src;
1747 target_ulong cc_src2;
1748 uint32_t cc_op;
1749 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
1750 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
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| /openbmc/qemu/target/mips/ |
| H A D | cpu.h | 528 typedef struct CPUArchState { struct
529 TCState active_tc;
530 CPUMIPSFPUContext active_fpu;
532 uint32_t current_tc;
534 uint32_t SEGBITS;
535 uint32_t PABITS;
541 target_ulong SEGMask;
542 uint64_t PAMask;
545 int32_t msair;
552 int32_t CP0_Index;
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| /openbmc/qemu/target/hppa/ |
| H A D | cpu.h | 203 typedef struct CPUArchState { struct
204 target_ulong iaoq_f; /* front */
205 target_ulong iaoq_b; /* back, aka next instruction */
207 target_ulong gr[32];
208 uint64_t fr[32];
209 uint64_t sr[8]; /* stored shifted into place for gva */
211 uint32_t psw; /* All psw bits except the following: */
212 uint32_t psw_xb; /* X and B, in their normal positions */
213 target_ulong psw_n; /* boolean */
214 target_long psw_v; /* in bit 31 */
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| /openbmc/qemu/target/alpha/ |
| H A D | cpu.h | 198 typedef struct CPUArchState { struct
199 uint64_t ir[31];
200 float64 fir[31];
201 uint64_t pc;
202 uint64_t unique;
203 uint64_t lock_addr;
204 uint64_t lock_value;
207 uint32_t fpcr;
209 uint32_t swcr;
211 uint32_t fpcr_exc_enable;
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| /openbmc/qemu/target/s390x/ |
| H A D | cpu.h | 55 typedef struct CPUArchState { struct
56 uint64_t regs[16]; /* GP registers */
61 uint64_t vregs[32][2] QEMU_ALIGNED(16); /* vector registers */
62 uint32_t aregs[16]; /* access registers */
63 uint64_t gscb[4]; /* guarded storage control */
64 uint64_t etoken; /* etoken */
65 uint64_t etoken_extension; /* etoken extension */
67 uint64_t diag318_info;
70 struct {} start_initial_reset_fields;
72 uint32_t fpc; /* floating-point control register */
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| /openbmc/qemu/target/m68k/ |
| H A D | cpu.h | 83 typedef struct CPUArchState { struct
84 uint32_t dregs[8];
85 uint32_t aregs[8];
86 uint32_t pc;
87 uint32_t sr;
96 int current_sp;
97 uint32_t sp[3];
100 uint32_t cc_op;
101 uint32_t cc_x; /* always 0/1 */
102 uint32_t cc_n; /* in bit 31 (i.e. negative) */
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| /openbmc/qemu/target/microblaze/ |
| H A D | cpu.h | 242 struct CPUArchState { struct
243 uint32_t bvalue; /* TCG temporary, only valid during a TB */
244 uint32_t btarget; /* Full resolved branch destination */
246 uint32_t imm;
247 uint32_t regs[32];
248 uint32_t pc;
249 uint32_t msr; /* All bits of MSR except MSR[C] and MSR[CC] */
250 uint32_t msr_c; /* MSR[C], in low bit; other bits must be 0 */
251 target_ulong ear;
252 uint32_t esr;
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| /openbmc/qemu/target/tricore/ |
| H A D | cpu.h | 29 typedef struct CPUArchState { struct
31 uint32_t gpr_a[16];
32 uint32_t gpr_d[16];
36 uint32_t PSW;
38 uint32_t PSW_USB_C;
39 uint32_t PSW_USB_V; /* Only if bit 31 set, then flag is set */
40 uint32_t PSW_USB_SV; /* Only if bit 31 set, then flag is set */
41 uint32_t PSW_USB_AV; /* Only if bit 31 set, then flag is set. */
42 uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */
53 float_status fp_status;
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| /openbmc/qemu/target/ppc/ |
| H A D | cpu.h | 1219 struct CPUArchState { struct
1221 target_ulong gpr[32]; /* general purpose registers */
1222 target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */
1223 target_ulong lr;
1224 target_ulong ctr;
1225 uint32_t crf[8]; /* condition register */
1227 target_ulong cfar;
1229 target_ulong xer; /* XER (with SO, OV, CA split out) */
1230 target_ulong so;
1231 target_ulong ov;
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| /openbmc/qemu/target/xtensa/ |
| H A D | cpu.h | 509 struct CPUArchState { struct
510 const XtensaConfig *config;
511 uint32_t regs[16];
512 uint32_t pc;
513 uint32_t sregs[256];
514 uint32_t uregs[256];
515 uint32_t phys_regs[MAX_NAREG];
516 union {
519 } fregs[16];
520 float_status fp_status;
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| /openbmc/qemu/target/arm/ |
| H A D | cpu.h | 205 typedef struct CPUArchState { struct
207 uint32_t regs[16];
214 uint64_t xregs[32];
215 uint64_t pc;
229 uint32_t pstate;
230 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */
231 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */
234 CPUARMTBFlags hflags;
239 uint32_t uncached_cpsr;
240 uint32_t spsr;
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| /openbmc/qemu/include/qemu/ |
| H A D | typedefs.h | 40 typedef struct CPUArchState CPUArchState; typedef
|