Home
last modified time | relevance | path

Searched defs:CONFIG_SYS_DDR_TIMING_5 (Results 1 – 9 of 9) sorted by relevance

/openbmc/u-boot/include/configs/
H A DBSC9132QDS.h171 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 macro
177 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 macro
183 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 macro
H A DBSC9131RDB.h99 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 macro
H A Dp1_twr.h98 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 macro
H A DUCP1020.h170 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 macro
H A DMPC8569MDS.h103 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 macro
H A DP1022DS.h163 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 macro
H A DP1010RDB.h240 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 macro
H A Dp1_p2_rdb_pc.h305 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 macro
/openbmc/u-boot/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c67 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 macro