Lines Matching +full:etheravb +full:- +full:r8a7795
1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2015-2017 Renesas Electronics Corporation
135 u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1); in ravb_invalidate_dcache()
143 struct ravb_desc *desc = ð->tx_desc[eth->tx_desc_idx]; in ravb_send()
149 desc->ctrl = RAVB_DESC_DT_FSINGLE | RAVB_DESC_DS(len); in ravb_send()
150 desc->dptr = (uintptr_t)packet; in ravb_send()
154 if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0)) in ravb_send()
155 setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0); in ravb_send()
161 if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE) in ravb_send()
167 return -ETIMEDOUT; in ravb_send()
169 eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1); in ravb_send()
176 struct ravb_rxdesc *desc = ð->rx_desc[eth->rx_desc_idx]; in ravb_recv()
182 if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY) in ravb_recv()
183 return -EAGAIN; in ravb_recv()
186 if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) { in ravb_recv()
187 desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK; in ravb_recv()
188 return -EAGAIN; in ravb_recv()
191 len = desc->data.ctrl & RAVB_DESC_DS_MASK; in ravb_recv()
192 packet = (u8 *)(uintptr_t)desc->data.dptr; in ravb_recv()
202 struct ravb_rxdesc *desc = ð->rx_desc[eth->rx_desc_idx]; in ravb_free_pkt()
205 desc->data.ctrl = RAVB_DESC_DT_FEMPTY | RAVB_DESC_DS(PKTSIZE_ALIGN); in ravb_free_pkt()
209 eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC; in ravb_free_pkt()
210 desc = ð->rx_desc[eth->rx_desc_idx]; in ravb_free_pkt()
221 writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC); in ravb_reset()
224 return wait_for_bit_le32(eth->iobase + RAVB_REG_CSR, in ravb_reset()
234 memset(eth->base_desc, 0x0, desc_size); in ravb_base_desc_init()
237 eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS; in ravb_base_desc_init()
239 ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size); in ravb_base_desc_init()
242 writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT); in ravb_base_desc_init()
251 memset(eth->tx_desc, 0x0, desc_size); in ravb_tx_desc_init()
252 eth->tx_desc_idx = 0; in ravb_tx_desc_init()
255 eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY; in ravb_tx_desc_init()
258 eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX; in ravb_tx_desc_init()
259 eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc; in ravb_tx_desc_init()
260 ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size); in ravb_tx_desc_init()
263 eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX; in ravb_tx_desc_init()
264 eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc; in ravb_tx_desc_init()
265 ravb_flush_dcache((uintptr_t)ð->base_desc[RAVB_TX_QUEUE_OFFSET], in ravb_tx_desc_init()
275 memset(eth->rx_desc, 0x0, desc_size); in ravb_rx_desc_init()
276 eth->rx_desc_idx = 0; in ravb_rx_desc_init()
279 eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY | in ravb_rx_desc_init()
281 eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet; in ravb_rx_desc_init()
283 eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX; in ravb_rx_desc_init()
284 eth->rx_desc[i].link.dptr = (uintptr_t)ð->rx_desc[i + 1]; in ravb_rx_desc_init()
288 eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX; in ravb_rx_desc_init()
289 eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc; in ravb_rx_desc_init()
290 ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size); in ravb_rx_desc_init()
293 eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX; in ravb_rx_desc_init()
294 eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc; in ravb_rx_desc_init()
295 ravb_flush_dcache((uintptr_t)ð->base_desc[RAVB_RX_QUEUE_OFFSET], in ravb_rx_desc_init()
306 if (dm_gpio_is_valid(ð->reset_gpio)) { in ravb_phy_config()
307 dm_gpio_set_value(ð->reset_gpio, 1); in ravb_phy_config()
309 dm_gpio_set_value(ð->reset_gpio, 0); in ravb_phy_config()
313 phydev = phy_find_by_mask(eth->bus, mask, pdata->phy_interface); in ravb_phy_config()
315 return -ENODEV; in ravb_phy_config()
319 eth->phydev = phydev; in ravb_phy_config()
321 phydev->supported &= SUPPORTED_100baseT_Full | in ravb_phy_config()
326 if (pdata->max_speed != 1000) { in ravb_phy_config()
327 phydev->supported &= ~SUPPORTED_1000baseT_Full; in ravb_phy_config()
328 reg = phy_read(phydev, -1, MII_CTRL1000); in ravb_phy_config()
330 phy_write(phydev, -1, MII_CTRL1000, reg); in ravb_phy_config()
343 unsigned char *mac = pdata->enetaddr; in ravb_write_hwaddr()
346 eth->iobase + RAVB_REG_MAHR); in ravb_write_hwaddr()
348 writel((mac[4] << 8) | mac[5], eth->iobase + RAVB_REG_MALR); in ravb_write_hwaddr()
353 /* E-MAC init function */
357 writel(0, eth->iobase + RAVB_REG_ECSIPR); in ravb_mac_init()
360 writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR); in ravb_mac_init()
365 /* AVB-DMAC init function */
378 writel(0, eth->iobase + RAVB_REG_RIC0); in ravb_dmac_init()
379 writel(0, eth->iobase + RAVB_REG_RIC1); in ravb_dmac_init()
380 writel(0, eth->iobase + RAVB_REG_RIC2); in ravb_dmac_init()
381 writel(0, eth->iobase + RAVB_REG_TIC); in ravb_dmac_init()
384 clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC); in ravb_dmac_init()
387 writel(0x18000001, eth->iobase + RAVB_REG_RCR); in ravb_dmac_init()
390 writel(0x00222210, eth->iobase + RAVB_REG_TGC); in ravb_dmac_init()
393 if (pdata->max_speed == 1000) in ravb_dmac_init()
394 writel(BIT(14), eth->iobase + RAVB_REG_APSR); in ravb_dmac_init()
402 struct phy_device *phy = eth->phydev; in ravb_config()
406 /* Configure AVB-DMAC register */ in ravb_config()
409 /* Configure E-MAC registers */ in ravb_config()
418 if (phy->speed == 100) in ravb_config()
419 writel(0, eth->iobase + RAVB_REG_GECMR); in ravb_config()
420 else if (phy->speed == 1000) in ravb_config()
421 writel(1, eth->iobase + RAVB_REG_GECMR); in ravb_config()
424 if (phy->duplex) in ravb_config()
427 writel(mask, eth->iobase + RAVB_REG_ECMR); in ravb_config()
429 phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f << 5) | 0x19); in ravb_config()
451 /* Setting the control will start the AVB-DMAC process. */ in ravb_start()
452 writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC); in ravb_start()
461 phy_shutdown(eth->phydev); in ravb_stop()
474 iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE); in ravb_probe()
475 eth->iobase = iobase; in ravb_probe()
477 ret = clk_get_by_index(dev, 0, ð->clk); in ravb_probe()
481 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &phandle_args); in ravb_probe()
483 gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0, in ravb_probe()
484 ð->reset_gpio, GPIOD_IS_OUT); in ravb_probe()
487 if (!dm_gpio_is_valid(ð->reset_gpio)) { in ravb_probe()
488 gpio_request_by_name(dev, "reset-gpios", 0, ð->reset_gpio, in ravb_probe()
494 ret = -ENOMEM; in ravb_probe()
498 mdiodev->read = bb_miiphy_read; in ravb_probe()
499 mdiodev->write = bb_miiphy_write; in ravb_probe()
501 snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name); in ravb_probe()
507 eth->bus = miiphy_get_dev_by_name(dev->name); in ravb_probe()
510 ret = clk_enable(ð->clk); in ravb_probe()
525 clk_disable(ð->clk); in ravb_probe()
529 unmap_physmem(eth->iobase, MAP_NOCACHE); in ravb_probe()
537 clk_disable(ð->clk); in ravb_remove()
539 free(eth->phydev); in ravb_remove()
540 mdio_unregister(eth->bus); in ravb_remove()
541 mdio_free(eth->bus); in ravb_remove()
542 if (dm_gpio_is_valid(ð->reset_gpio)) in ravb_remove()
543 dm_gpio_free(dev, ð->reset_gpio); in ravb_remove()
544 unmap_physmem(eth->iobase, MAP_NOCACHE); in ravb_remove()
556 struct ravb_priv *eth = bus->priv; in ravb_bb_mdio_active()
558 setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD); in ravb_bb_mdio_active()
565 struct ravb_priv *eth = bus->priv; in ravb_bb_mdio_tristate()
567 clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD); in ravb_bb_mdio_tristate()
574 struct ravb_priv *eth = bus->priv; in ravb_bb_set_mdio()
577 setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO); in ravb_bb_set_mdio()
579 clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO); in ravb_bb_set_mdio()
586 struct ravb_priv *eth = bus->priv; in ravb_bb_get_mdio()
588 *v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3; in ravb_bb_get_mdio()
595 struct ravb_priv *eth = bus->priv; in ravb_bb_set_mdc()
598 setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC); in ravb_bb_set_mdc()
600 clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC); in ravb_bb_set_mdc()
642 pdata->iobase = devfdt_get_addr(dev); in ravb_ofdata_to_platdata()
643 pdata->phy_interface = -1; in ravb_ofdata_to_platdata()
644 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", in ravb_ofdata_to_platdata()
647 pdata->phy_interface = phy_get_interface_by_name(phy_mode); in ravb_ofdata_to_platdata()
648 if (pdata->phy_interface == -1) { in ravb_ofdata_to_platdata()
650 return -EINVAL; in ravb_ofdata_to_platdata()
653 pdata->max_speed = 1000; in ravb_ofdata_to_platdata()
654 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL); in ravb_ofdata_to_platdata()
656 pdata->max_speed = fdt32_to_cpu(*cell); in ravb_ofdata_to_platdata()
658 sprintf(bb_miiphy_buses[0].name, dev->name); in ravb_ofdata_to_platdata()
664 { .compatible = "renesas,etheravb-r8a7795" },
665 { .compatible = "renesas,etheravb-r8a7796" },
666 { .compatible = "renesas,etheravb-r8a77965" },
667 { .compatible = "renesas,etheravb-r8a77970" },
668 { .compatible = "renesas,etheravb-r8a77990" },
669 { .compatible = "renesas,etheravb-r8a77995" },
670 { .compatible = "renesas,etheravb-rcar-gen3" },