1 // SPDX-License-Identifier: GPL-2.0+
3  * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
4  * (C) Copyright 2018 - BayLibre, SAS
9 #include <asm/arch/clock-gx.h>
11 #include <clk-uclass.h>
16 #include <dt-bindings/clock/gxbb-clkc.h>
20  * - Can calculate clock frequency on a limited tree
21  * - Can Read muxes and basic dividers (0-based only)
22  * - Can enable/disable gates with limited propagation
23  * - Can reparent without propagation, only on muxes
24  * - Can set rates without reparenting
25  * This driver is adapted to what is actually supported by U-Boot
197 	struct meson_clk *priv = dev_get_priv(clk->dev);  in meson_set_gate_by_id()
213 		return -ENOENT;  in meson_set_gate_by_id()
217 	if (gate->reg == 0)  in meson_set_gate_by_id()
222 	regmap_update_bits(priv->map, gate->reg,  in meson_set_gate_by_id()
223 			   BIT(gate->bit), on ? BIT(gate->bit) : 0);  in meson_set_gate_by_id()
236 	return meson_set_gate_by_id(clk, clk->id, true);  in meson_clk_enable()
241 	return meson_set_gate_by_id(clk, clk->id, false);  in meson_clk_disable()
270 	struct meson_clk *priv = dev_get_priv(clk->dev);  in meson_div_get_rate()
294 		return -ENOENT;  in meson_div_get_rate()
297 	regmap_read(priv->map, parm->reg_off, &reg);  in meson_div_get_rate()
298 	reg = PARM_GET(parm->width, parm->shift, reg);  in meson_div_get_rate()
318 	struct meson_clk *priv = dev_get_priv(clk->dev);  in meson_div_set_rate()
319 	unsigned int new_div = -EINVAL;  in meson_div_set_rate()
349 		return -ENOENT;  in meson_div_set_rate()
368 	if (!new_div || new_div > (1 << parm->width)) {  in meson_div_set_rate()
381 		if (!new_div || new_div > (1 << parm->width))  in meson_div_set_rate()
382 			return -EINVAL;  in meson_div_set_rate()
387 	regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift),  in meson_div_set_rate()
388 			   (new_div - 1) << parm->shift);  in meson_div_set_rate()
446 	struct meson_clk *priv = dev_get_priv(clk->dev);  in meson_mux_get_parent()
477 		return -ENOENT;  in meson_mux_get_parent()
480 	regmap_read(priv->map, parm->reg_off, &reg);  in meson_mux_get_parent()
481 	reg = PARM_GET(parm->width, parm->shift, reg);  in meson_mux_get_parent()
493 	struct meson_clk *priv = dev_get_priv(clk->dev);  in meson_mux_set_parent()
494 	unsigned int new_index = -EINVAL;  in meson_mux_set_parent()
535 		return -ENOENT;  in meson_mux_set_parent()
538 	for (i = 0 ; i < (1 << parm->width) ; ++i) {  in meson_mux_set_parent()
548 	regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift),  in meson_mux_set_parent()
549 			   new_index << parm->shift);  in meson_mux_set_parent()
569 	struct meson_clk *priv = dev_get_priv(clk->dev);  in meson_clk81_get_rate()
573 		-1,  in meson_clk81_get_rate()
574 		-1,  in meson_clk81_get_rate()
584 	regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);  in meson_clk81_get_rate()
592 		return -ENOENT;  in meson_clk81_get_rate()
598 	regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);  in meson_clk81_get_rate()
599 	reg = reg & ((1 << 7) - 1);  in meson_clk81_get_rate()
612 		return -EINVAL;  in mpll_rate_from_params()
640 	struct meson_clk *priv = dev_get_priv(clk->dev);  in meson_mpll_get_rate()
660 		return -ENOENT;  in meson_mpll_get_rate()
667 	regmap_read(priv->map, psdm->reg_off, &reg);  in meson_mpll_get_rate()
668 	sdm = PARM_GET(psdm->width, psdm->shift, reg);  in meson_mpll_get_rate()
670 	regmap_read(priv->map, pn2->reg_off, &reg);  in meson_mpll_get_rate()
671 	n2 = PARM_GET(pn2->width, pn2->shift, reg);  in meson_mpll_get_rate()
690 	struct meson_clk *priv = dev_get_priv(clk->dev);  in meson_pll_get_rate()
708 		return -ENOENT;  in meson_pll_get_rate()
711 	regmap_read(priv->map, pn->reg_off, &reg);  in meson_pll_get_rate()
712 	n = PARM_GET(pn->width, pn->shift, reg);  in meson_pll_get_rate()
714 	regmap_read(priv->map, pm->reg_off, &reg);  in meson_pll_get_rate()
715 	m = PARM_GET(pm->width, pm->shift, reg);  in meson_pll_get_rate()
717 	regmap_read(priv->map, pod->reg_off, &reg);  in meson_pll_get_rate()
718 	od = PARM_GET(pod->width, pod->shift, reg);  in meson_pll_get_rate()
790 		return -ENOENT;  in meson_clk_get_rate_by_id()
799 	return meson_clk_get_rate_by_id(clk, clk->id);  in meson_clk_get_rate()
804 	return meson_mux_set_parent(clk, clk->id, parent->id);  in meson_clk_set_parent()
827 			return -EINVAL;  in meson_clk_set_rate_by_id()
857 		return -ENOENT;  in meson_clk_set_rate_by_id()
860 	return -EINVAL;  in meson_clk_set_rate_by_id()
865 	ulong current_rate = meson_clk_get_rate_by_id(clk, clk->id);  in meson_clk_set_rate()
872 	      __func__, clk->id, current_rate, rate);  in meson_clk_set_rate()
874 	ret = meson_clk_set_rate_by_id(clk, clk->id, rate, current_rate);  in meson_clk_set_rate()
878 	debug("clock %lu has new rate %lu\n", clk->id,  in meson_clk_set_rate()
879 	      meson_clk_get_rate_by_id(clk, clk->id));  in meson_clk_set_rate()
888 	priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);  in meson_clk_probe()
889 	if (IS_ERR(priv->map))  in meson_clk_probe()
890 		return PTR_ERR(priv->map);  in meson_clk_probe()
892 	debug("meson-clk: probed\n");  in meson_clk_probe()
906 	{ .compatible = "amlogic,gxbb-clkc" },
907 	{ .compatible = "amlogic,gxl-clkc" },