Lines Matching +full:spi0 +full:- +full:pins

4  * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/thermal/thermal.h>
49 #include <dt-bindings/memory/rk3368-dmc.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <2>;
55 #size-cells = <2>;
70 spi0 = &spi0;
76 #address-cells = <0x2>;
77 #size-cells = <0x0>;
79 cpu-map {
111 idle-states {
112 entry-method = "psci";
114 cpu_sleep: cpu-sleep-0 {
115 compatible = "arm,idle-state";
116 arm,psci-suspend-param = <0x1010000>;
117 entry-latency-us = <0x3fffffff>;
118 exit-latency-us = <0x40000000>;
119 min-residency-us = <0xffffffff>;
125 compatible = "arm,cortex-a53", "arm,armv8";
127 cpu-idle-states = <&cpu_sleep>;
128 enable-method = "psci";
130 #cooling-cells = <2>; /* min followed by max */
135 compatible = "arm,cortex-a53", "arm,armv8";
137 cpu-idle-states = <&cpu_sleep>;
138 enable-method = "psci";
143 compatible = "arm,cortex-a53", "arm,armv8";
145 cpu-idle-states = <&cpu_sleep>;
146 enable-method = "psci";
151 compatible = "arm,cortex-a53", "arm,armv8";
153 cpu-idle-states = <&cpu_sleep>;
154 enable-method = "psci";
159 compatible = "arm,cortex-a53", "arm,armv8";
161 cpu-idle-states = <&cpu_sleep>;
162 enable-method = "psci";
164 #cooling-cells = <2>; /* min followed by max */
169 compatible = "arm,cortex-a53", "arm,armv8";
171 cpu-idle-states = <&cpu_sleep>;
172 enable-method = "psci";
177 compatible = "arm,cortex-a53", "arm,armv8";
179 cpu-idle-states = <&cpu_sleep>;
180 enable-method = "psci";
185 compatible = "arm,cortex-a53", "arm,armv8";
187 cpu-idle-states = <&cpu_sleep>;
188 enable-method = "psci";
192 arm-pmu {
193 compatible = "arm,armv8-pmuv3";
202 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
208 compatible = "arm,psci-0.2";
213 compatible = "arm,armv8-timer";
225 compatible = "fixed-clock";
226 clock-frequency = <24000000>;
227 clock-output-names = "xin24m";
228 #clock-cells = <0>;
232 compatible = "rockchip,rk3368-dmc", "syscon";
241 compatible = "rockchip,rk3368-msch", "syscon";
247 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
249 clock-freq-min-max = <400000 150000000>;
252 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
253 fifo-depth = <0x100>;
259 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
261 clock-freq-min-max = <400000 150000000>;
264 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
265 fifo-depth = <0x100>;
271 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
273 clock-freq-min-max = <400000 150000000>;
276 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
277 fifo-depth = <0x100>;
286 #io-channel-cells = <1>;
288 clock-names = "saradc", "apb_pclk";
292 spi0: spi@ff110000 { label
293 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
296 clock-names = "spiclk", "apb_pclk";
298 pinctrl-names = "default";
299 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
300 #address-cells = <1>;
301 #size-cells = <0>;
306 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
309 clock-names = "spiclk", "apb_pclk";
311 pinctrl-names = "default";
312 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
313 #address-cells = <1>;
314 #size-cells = <0>;
319 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
322 clock-names = "spiclk", "apb_pclk";
324 pinctrl-names = "default";
325 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
326 #address-cells = <1>;
327 #size-cells = <0>;
332 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
335 #address-cells = <1>;
336 #size-cells = <0>;
337 clock-names = "i2c";
339 pinctrl-names = "default";
340 pinctrl-0 = <&i2c1_xfer>;
345 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
348 #address-cells = <1>;
349 #size-cells = <0>;
350 clock-names = "i2c";
352 pinctrl-names = "default";
353 pinctrl-0 = <&i2c3_xfer>;
358 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
361 #address-cells = <1>;
362 #size-cells = <0>;
363 clock-names = "i2c";
365 pinctrl-names = "default";
366 pinctrl-0 = <&i2c4_xfer>;
371 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
374 #address-cells = <1>;
375 #size-cells = <0>;
376 clock-names = "i2c";
378 pinctrl-names = "default";
379 pinctrl-0 = <&i2c5_xfer>;
384 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
386 clock-frequency = <24000000>;
388 clock-names = "baudclk", "apb_pclk";
390 reg-shift = <2>;
391 reg-io-width = <4>;
392 pinctrl-names = "default";
393 pinctrl-0 = <&uart0_xfer>;
398 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
400 clock-frequency = <24000000>;
402 clock-names = "baudclk", "apb_pclk";
404 reg-shift = <2>;
405 reg-io-width = <4>;
406 pinctrl-names = "default";
407 pinctrl-1 = <&uart0_xfer>;
412 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
414 clock-frequency = <24000000>;
416 clock-names = "baudclk", "apb_pclk";
418 reg-shift = <2>;
419 reg-io-width = <4>;
420 pinctrl-names = "default";
421 pinctrl-0 = <&uart3_xfer>;
426 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
428 clock-frequency = <24000000>;
430 clock-names = "baudclk", "apb_pclk";
432 reg-shift = <2>;
433 reg-io-width = <4>;
434 pinctrl-names = "default";
435 pinctrl-0 = <&uart4_xfer>;
439 thermal-zones {
441 polling-delay-passive = <100>; /* milliseconds */
442 polling-delay = <5000>; /* milliseconds */
444 thermal-sensors = <&tsadc 0>;
464 cooling-maps {
467 cooling-device =
472 cooling-device =
479 polling-delay-passive = <100>; /* milliseconds */
480 polling-delay = <5000>; /* milliseconds */
482 thermal-sensors = <&tsadc 1>;
497 cooling-maps {
500 cooling-device =
508 compatible = "rockchip,rk3368-tsadc";
512 clock-names = "tsadc", "apb_pclk";
514 reset-names = "tsadc-apb";
515 pinctrl-names = "init", "default", "sleep";
516 pinctrl-0 = <&otp_gpio>;
517 pinctrl-1 = <&otp_out>;
518 pinctrl-2 = <&otp_gpio>;
519 #thermal-sensor-cells = <1>;
520 rockchip,hw-tshut-temp = <95000>;
525 compatible = "rockchip,rk3368-gmac";
528 interrupt-names = "macirq";
534 clock-names = "stmmaceth",
542 compatible = "generic-ehci";
546 clock-names = "usbhost";
551 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
556 clock-names = "otg";
558 g-np-tx-fifo-size = <16>;
559 g-rx-fifo-size = <275>;
560 g-tx-fifo-size = <256 128 128 64 64 32>;
561 g-use-dma;
566 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
569 clock-names = "i2c";
571 pinctrl-names = "default";
572 pinctrl-0 = <&i2c0_xfer>;
573 #address-cells = <1>;
574 #size-cells = <0>;
579 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
582 #address-cells = <1>;
583 #size-cells = <0>;
584 clock-names = "i2c";
586 pinctrl-names = "default";
587 pinctrl-0 = <&i2c2_xfer>;
592 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
594 #pwm-cells = <3>;
595 pinctrl-names = "default";
596 pinctrl-0 = <&pwm0_pin>;
598 clock-names = "pwm";
603 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
605 #pwm-cells = <3>;
606 pinctrl-names = "default";
607 pinctrl-0 = <&pwm1_pin>;
609 clock-names = "pwm";
614 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
616 #pwm-cells = <3>;
618 clock-names = "pwm";
623 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
625 #pwm-cells = <3>;
626 pinctrl-names = "default";
627 pinctrl-0 = <&pwm3_pin>;
629 clock-names = "pwm";
634 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
636 clock-frequency = <24000000>;
638 clock-names = "baudclk", "apb_pclk";
640 pinctrl-names = "default";
641 pinctrl-0 = <&uart2_xfer>;
642 reg-shift = <2>;
643 reg-io-width = <4>;
648 compatible = "rockchip,rk3368-mailbox";
655 clock-names = "pclk_mailbox";
656 #mbox-cells = <1>;
660 compatible = "rockchip,rk3368-pmugrf", "syscon";
665 compatible = "rockchip,rk3368-sgrf", "syscon";
669 cru: clock-controller@ff760000 {
670 compatible = "rockchip,rk3368-cru";
673 #clock-cells = <1>;
674 #reset-cells = <1>;
678 compatible = "rockchip,rk3368-grf", "syscon";
683 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
691 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
696 gic: interrupt-controller@ffb71000 {
697 compatible = "arm,gic-400";
698 interrupt-controller;
699 #interrupt-cells = <3>;
700 #address-cells = <0>;
711 compatible = "rockchip,rk3368-pinctrl";
714 #address-cells = <0x2>;
715 #size-cells = <0x2>;
719 compatible = "rockchip,gpio-bank";
724 gpio-controller;
725 #gpio-cells = <0x2>;
727 interrupt-controller;
728 #interrupt-cells = <0x2>;
732 compatible = "rockchip,gpio-bank";
737 gpio-controller;
738 #gpio-cells = <0x2>;
740 interrupt-controller;
741 #interrupt-cells = <0x2>;
745 compatible = "rockchip,gpio-bank";
750 gpio-controller;
751 #gpio-cells = <0x2>;
753 interrupt-controller;
754 #interrupt-cells = <0x2>;
758 compatible = "rockchip,gpio-bank";
763 gpio-controller;
764 #gpio-cells = <0x2>;
766 interrupt-controller;
767 #interrupt-cells = <0x2>;
770 pcfg_pull_up: pcfg-pull-up {
771 bias-pull-up;
774 pcfg_pull_down: pcfg-pull-down {
775 bias-pull-down;
778 pcfg_pull_none: pcfg-pull-none {
779 bias-disable;
782 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
783 bias-disable;
784 drive-strength = <12>;
788 emmc_clk: emmc-clk {
789 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
792 emmc_cmd: emmc-cmd {
793 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
796 emmc_pwr: emmc-pwr {
797 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
800 emmc_bus1: emmc-bus1 {
801 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
804 emmc_bus4: emmc-bus4 {
805 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
811 emmc_bus8: emmc-bus8 {
812 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
824 rgmii_pins: rgmii-pins {
825 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
842 rmii_pins: rmii-pins {
843 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
857 i2c0_xfer: i2c0-xfer {
858 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
864 i2c1_xfer: i2c1-xfer {
865 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
871 i2c2_xfer: i2c2-xfer {
872 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
878 i2c3_xfer: i2c3-xfer {
879 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
885 i2c4_xfer: i2c4-xfer {
886 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
892 i2c5_xfer: i2c5-xfer {
893 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
899 pwm0_pin: pwm0-pin {
900 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
905 pwm1_pin: pwm1-pin {
906 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
911 pwm3_pin: pwm3-pin {
912 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
917 sdio0_bus1: sdio0-bus1 {
918 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
921 sdio0_bus4: sdio0-bus4 {
922 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
928 sdio0_cmd: sdio0-cmd {
929 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
932 sdio0_clk: sdio0-clk {
933 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
936 sdio0_cd: sdio0-cd {
937 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
940 sdio0_wp: sdio0-wp {
941 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
944 sdio0_pwr: sdio0-pwr {
945 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
948 sdio0_bkpwr: sdio0-bkpwr {
949 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
952 sdio0_int: sdio0-int {
953 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
958 sdmmc_clk: sdmmc-clk {
959 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
962 sdmmc_cmd: sdmmc-cmd {
963 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
966 sdmmc_cd: sdmmc-cd {
967 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
970 sdmmc_bus1: sdmmc-bus1 {
971 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
974 sdmmc_bus4: sdmmc-bus4 {
975 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
982 spi0 {
983 spi0_clk: spi0-clk {
984 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
986 spi0_cs0: spi0-cs0 {
987 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
989 spi0_cs1: spi0-cs1 {
990 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
992 spi0_tx: spi0-tx {
993 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
995 spi0_rx: spi0-rx {
996 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1001 spi1_clk: spi1-clk {
1002 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1004 spi1_cs0: spi1-cs0 {
1005 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1007 spi1_cs1: spi1-cs1 {
1008 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1010 spi1_rx: spi1-rx {
1011 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1013 spi1_tx: spi1-tx {
1014 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1019 spi2_clk: spi2-clk {
1020 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1022 spi2_cs0: spi2-cs0 {
1023 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1025 spi2_rx: spi2-rx {
1026 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1028 spi2_tx: spi2-tx {
1029 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1034 otp_gpio: otp-gpio {
1035 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1038 otp_out: otp-out {
1039 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1044 uart0_xfer: uart0-xfer {
1045 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1049 uart0_cts: uart0-cts {
1050 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1053 uart0_rts: uart0-rts {
1054 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1059 uart1_xfer: uart1-xfer {
1060 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1064 uart1_cts: uart1-cts {
1065 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1068 uart1_rts: uart1-rts {
1069 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1074 uart2_xfer: uart2-xfer {
1075 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1082 uart3_xfer: uart3-xfer {
1083 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1087 uart3_cts: uart3-cts {
1088 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1091 uart3_rts: uart3-rts {
1092 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1097 uart4_xfer: uart4-xfer {
1098 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1102 uart4_cts: uart4-cts {
1103 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1106 uart4_rts: uart4-rts {
1107 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;