Lines Matching +full:cs +full:- +full:1
18 #include "qemu/main-loop.h"
24 #include "target/arm/cpu-features.h"
37 return env->gicv3state; in icc_cs_from_env()
51 static inline int icv_min_vbpr(GICv3CPUState *cs) in icv_min_vbpr() argument
53 return 7 - cs->vprebits; in icv_min_vbpr()
56 static inline int ich_num_aprs(GICv3CPUState *cs) in ich_num_aprs() argument
58 /* Return the number of virtual APR registers (1, 2, or 4) */ in ich_num_aprs()
59 int aprmax = 1 << (cs->vprebits - 5); in ich_num_aprs()
60 assert(aprmax <= ARRAY_SIZE(cs->ich_apr[0])); in ich_num_aprs()
94 * * access if NS EL1 and HCR_EL2.FMO == 1: in icv_access()
96 * * access if NS EL1 and HCR_EL2.IMO == 1: in icv_access()
97 * all ICV regs with '1' in their name in icv_access()
98 * * access if NS EL1 and either IMO or FMO == 1: in icv_access()
104 return flagmatch && arm_current_el(env) == 1 in icv_access()
108 static int read_vbpr(GICv3CPUState *cs, int grp) in read_vbpr() argument
114 return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in read_vbpr()
117 return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR1_SHIFT, in read_vbpr()
122 static void write_vbpr(GICv3CPUState *cs, int grp, int value) in write_vbpr() argument
127 int min = icv_min_vbpr(cs); in write_vbpr()
136 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in write_vbpr()
139 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR1_SHIFT, in write_vbpr()
144 static uint32_t icv_fullprio_mask(GICv3CPUState *cs) in icv_fullprio_mask() argument
151 return (~0U << (8 - cs->vpribits)) & 0xff; in icv_fullprio_mask()
154 static int ich_highest_active_virt_prio(GICv3CPUState *cs) in ich_highest_active_virt_prio() argument
160 int aprmax = ich_num_aprs(cs); in ich_highest_active_virt_prio()
162 if (cs->ich_apr[GICV3_G1NS][0] & ICV_AP1R_EL1_NMI) { in ich_highest_active_virt_prio()
167 uint32_t apr = cs->ich_apr[GICV3_G0][i] | in ich_highest_active_virt_prio()
168 cs->ich_apr[GICV3_G1NS][i]; in ich_highest_active_virt_prio()
173 return (i * 32 + ctz32(apr)) << (icv_min_vbpr(cs) + 1); in ich_highest_active_virt_prio()
179 static int hppvi_index(GICv3CPUState *cs) in hppvi_index() argument
184 * pseudocode. If no pending virtual interrupts, return -1. in hppvi_index()
191 ARMCPU *cpu = ARM_CPU(cs->cpu); in hppvi_index()
192 CPUARMState *env = &cpu->env; in hppvi_index()
193 int idx = -1; in hppvi_index()
202 if (!(cs->ich_vmcr_el2 & (ICH_VMCR_EL2_VENG0 | ICH_VMCR_EL2_VENG1))) { in hppvi_index()
207 for (i = 0; i < cs->num_list_regs; i++) { in hppvi_index()
208 uint64_t lr = cs->ich_lr_el2[i]; in hppvi_index()
219 if (!(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) { in hppvi_index()
223 if (!(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG0)) { in hppvi_index()
241 * when we are in Non-Secure state. in hppvi_index()
243 if (cs->hppvlpi.prio < prio && !arm_is_secure(env)) { in hppvi_index()
244 if (cs->hppvlpi.grp == GICV3_G0) { in hppvi_index()
245 if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG0) { in hppvi_index()
249 if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1) { in hppvi_index()
258 static uint32_t icv_gprio_mask(GICv3CPUState *cs, int group) in icv_gprio_mask() argument
264 * a BPR of 0 means the group priority bits are [7:1]; in icv_gprio_mask()
265 * a BPR of 1 means they are [7:2], and so on down to in icv_gprio_mask()
268 * a BPR of 0 is impossible (the minimum value is 1) in icv_gprio_mask()
269 * a BPR of 1 means the group priority bits are [7:1]; in icv_gprio_mask()
280 if (group == GICV3_G1NS && cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR) { in icv_gprio_mask()
284 bpr = read_vbpr(cs, group); in icv_gprio_mask()
287 bpr--; in icv_gprio_mask()
290 return ~0U << (bpr + 1); in icv_gprio_mask()
293 static bool icv_hppi_can_preempt(GICv3CPUState *cs, uint64_t lr) in icv_hppi_can_preempt() argument
298 * Compare also icc_hppi_can_preempt() which is the non-virtual in icv_hppi_can_preempt()
305 if (!(cs->ich_hcr_el2 & ICH_HCR_EL2_EN)) { in icv_hppi_can_preempt()
316 vpmr = extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT, in icv_hppi_can_preempt()
324 rprio = ich_highest_active_virt_prio(cs); in icv_hppi_can_preempt()
332 mask = icv_gprio_mask(cs, grp); in icv_hppi_can_preempt()
342 !(cs->ich_apr[GICV3_G1NS][0] & ICV_AP1R_EL1_NMI)) { in icv_hppi_can_preempt()
349 static bool icv_hppvlpi_can_preempt(GICv3CPUState *cs) in icv_hppvlpi_can_preempt() argument
353 * We can assume we're Non-secure because hppvi_index() already in icv_hppvlpi_can_preempt()
358 if (!(cs->ich_hcr_el2 & ICH_HCR_EL2_EN)) { in icv_hppvlpi_can_preempt()
363 vpmr = extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT, in icv_hppvlpi_can_preempt()
366 if (cs->hppvlpi.prio >= vpmr) { in icv_hppvlpi_can_preempt()
371 rprio = ich_highest_active_virt_prio(cs); in icv_hppvlpi_can_preempt()
377 mask = icv_gprio_mask(cs, cs->hppvlpi.grp); in icv_hppvlpi_can_preempt()
383 if ((cs->hppvlpi.prio & mask) < (rprio & mask)) { in icv_hppvlpi_can_preempt()
390 static uint32_t eoi_maintenance_interrupt_state(GICv3CPUState *cs, in eoi_maintenance_interrupt_state() argument
395 * 1 if LR.State == 0 && LR.HW == 0 && LR.EOI == 1 in eoi_maintenance_interrupt_state()
405 for (i = 0; i < cs->num_list_regs; i++) { in eoi_maintenance_interrupt_state()
406 uint64_t lr = cs->ich_lr_el2[i]; in eoi_maintenance_interrupt_state()
410 value |= (1 << i); in eoi_maintenance_interrupt_state()
421 if (validcount < 2 && (cs->ich_hcr_el2 & ICH_HCR_EL2_UIE)) { in eoi_maintenance_interrupt_state()
424 if (!seenpending && (cs->ich_hcr_el2 & ICH_HCR_EL2_NPIE)) { in eoi_maintenance_interrupt_state()
434 static uint32_t maintenance_interrupt_state(GICv3CPUState *cs) in maintenance_interrupt_state() argument
442 eoi_maintenance_interrupt_state(cs, &value); in maintenance_interrupt_state()
444 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_LRENPIE) && in maintenance_interrupt_state()
445 (cs->ich_hcr_el2 & ICH_HCR_EL2_EOICOUNT_MASK)) { in maintenance_interrupt_state()
449 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP0EIE) && in maintenance_interrupt_state()
450 (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG0)) { in maintenance_interrupt_state()
454 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP0DIE) && in maintenance_interrupt_state()
455 !(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) { in maintenance_interrupt_state()
458 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP1EIE) && in maintenance_interrupt_state()
459 (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) { in maintenance_interrupt_state()
463 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP1DIE) && in maintenance_interrupt_state()
464 !(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) { in maintenance_interrupt_state()
471 void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs) in gicv3_cpuif_virt_irq_fiq_update() argument
487 idx = hppvi_index(cs); in gicv3_cpuif_virt_irq_fiq_update()
488 trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx, in gicv3_cpuif_virt_irq_fiq_update()
489 cs->hppvlpi.irq, cs->hppvlpi.grp, in gicv3_cpuif_virt_irq_fiq_update()
490 cs->hppvlpi.prio); in gicv3_cpuif_virt_irq_fiq_update()
492 if (icv_hppvlpi_can_preempt(cs)) { in gicv3_cpuif_virt_irq_fiq_update()
493 if (cs->hppvlpi.grp == GICV3_G0) { in gicv3_cpuif_virt_irq_fiq_update()
494 fiqlevel = 1; in gicv3_cpuif_virt_irq_fiq_update()
496 irqlevel = 1; in gicv3_cpuif_virt_irq_fiq_update()
500 uint64_t lr = cs->ich_lr_el2[idx]; in gicv3_cpuif_virt_irq_fiq_update()
502 if (icv_hppi_can_preempt(cs, lr)) { in gicv3_cpuif_virt_irq_fiq_update()
506 * non-maskable property. in gicv3_cpuif_virt_irq_fiq_update()
510 nmilevel = 1; in gicv3_cpuif_virt_irq_fiq_update()
512 irqlevel = 1; in gicv3_cpuif_virt_irq_fiq_update()
515 fiqlevel = 1; in gicv3_cpuif_virt_irq_fiq_update()
520 trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs), fiqlevel, irqlevel); in gicv3_cpuif_virt_irq_fiq_update()
521 qemu_set_irq(cs->parent_vfiq, fiqlevel); in gicv3_cpuif_virt_irq_fiq_update()
522 qemu_set_irq(cs->parent_virq, irqlevel); in gicv3_cpuif_virt_irq_fiq_update()
523 qemu_set_irq(cs->parent_vnmi, nmilevel); in gicv3_cpuif_virt_irq_fiq_update()
526 static void gicv3_cpuif_virt_update(GICv3CPUState *cs) in gicv3_cpuif_virt_update() argument
535 * to the GIC as a per-CPU interrupt. This means that it in gicv3_cpuif_virt_update()
546 ARMCPU *cpu = ARM_CPU(cs->cpu); in gicv3_cpuif_virt_update()
549 gicv3_cpuif_virt_irq_fiq_update(cs); in gicv3_cpuif_virt_update()
551 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_EN) && in gicv3_cpuif_virt_update()
552 maintenance_interrupt_state(cs) != 0) { in gicv3_cpuif_virt_update()
553 maintlevel = 1; in gicv3_cpuif_virt_update()
556 trace_gicv3_cpuif_virt_set_maint_irq(gicv3_redist_affid(cs), maintlevel); in gicv3_cpuif_virt_update()
557 qemu_set_irq(cpu->gicv3_maintenance_interrupt, maintlevel); in gicv3_cpuif_virt_update()
562 GICv3CPUState *cs = icc_cs_from_env(env); in icv_ap_read() local
563 int regno = ri->opc2 & 3; in icv_ap_read()
564 int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; in icv_ap_read()
565 uint64_t value = cs->ich_apr[grp][regno]; in icv_ap_read()
567 trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value); in icv_ap_read()
574 GICv3CPUState *cs = icc_cs_from_env(env); in icv_ap_write() local
575 int regno = ri->opc2 & 3; in icv_ap_write()
576 int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; in icv_ap_write()
578 trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); in icv_ap_write()
580 if (cs->nmi_support) { in icv_ap_write()
581 cs->ich_apr[grp][regno] = value & (0xFFFFFFFFU | ICV_AP1R_EL1_NMI); in icv_ap_write()
583 cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU; in icv_ap_write()
586 gicv3_cpuif_virt_irq_fiq_update(cs); in icv_ap_write()
592 GICv3CPUState *cs = icc_cs_from_env(env); in icv_bpr_read() local
593 int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1NS; in icv_bpr_read()
597 if (grp == GICV3_G1NS && (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) { in icv_bpr_read()
598 /* reads return bpr0 + 1 saturated to 7, writes ignored */ in icv_bpr_read()
603 bpr = read_vbpr(cs, grp); in icv_bpr_read()
610 trace_gicv3_icv_bpr_read(ri->crm == 8 ? 0 : 1, gicv3_redist_affid(cs), bpr); in icv_bpr_read()
618 GICv3CPUState *cs = icc_cs_from_env(env); in icv_bpr_write() local
619 int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1NS; in icv_bpr_write()
621 trace_gicv3_icv_bpr_write(ri->crm == 8 ? 0 : 1, in icv_bpr_write()
622 gicv3_redist_affid(cs), value); in icv_bpr_write()
624 if (grp == GICV3_G1NS && (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) { in icv_bpr_write()
625 /* reads return bpr0 + 1 saturated to 7, writes ignored */ in icv_bpr_write()
629 write_vbpr(cs, grp, value); in icv_bpr_write()
631 gicv3_cpuif_virt_irq_fiq_update(cs); in icv_bpr_write()
636 GICv3CPUState *cs = icc_cs_from_env(env); in icv_pmr_read() local
639 value = extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT, in icv_pmr_read()
642 trace_gicv3_icv_pmr_read(gicv3_redist_affid(cs), value); in icv_pmr_read()
649 GICv3CPUState *cs = icc_cs_from_env(env); in icv_pmr_write() local
651 trace_gicv3_icv_pmr_write(gicv3_redist_affid(cs), value); in icv_pmr_write()
653 value &= icv_fullprio_mask(cs); in icv_pmr_write()
655 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT, in icv_pmr_write()
658 gicv3_cpuif_virt_irq_fiq_update(cs); in icv_pmr_write()
663 GICv3CPUState *cs = icc_cs_from_env(env); in icv_igrpen_read() local
667 enbit = ri->opc2 & 1 ? ICH_VMCR_EL2_VENG1_SHIFT : ICH_VMCR_EL2_VENG0_SHIFT; in icv_igrpen_read()
668 value = extract64(cs->ich_vmcr_el2, enbit, 1); in icv_igrpen_read()
670 trace_gicv3_icv_igrpen_read(ri->opc2 & 1 ? 1 : 0, in icv_igrpen_read()
671 gicv3_redist_affid(cs), value); in icv_igrpen_read()
678 GICv3CPUState *cs = icc_cs_from_env(env); in icv_igrpen_write() local
681 trace_gicv3_icv_igrpen_write(ri->opc2 & 1 ? 1 : 0, in icv_igrpen_write()
682 gicv3_redist_affid(cs), value); in icv_igrpen_write()
684 enbit = ri->opc2 & 1 ? ICH_VMCR_EL2_VENG1_SHIFT : ICH_VMCR_EL2_VENG0_SHIFT; in icv_igrpen_write()
686 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, enbit, 1, value); in icv_igrpen_write()
687 gicv3_cpuif_virt_update(cs); in icv_igrpen_write()
692 GICv3CPUState *cs = icc_cs_from_env(env); in icv_ctlr_read() local
698 value = ICC_CTLR_EL1_A3V | (1 << ICC_CTLR_EL1_IDBITS_SHIFT) | in icv_ctlr_read()
699 ((cs->vpribits - 1) << ICC_CTLR_EL1_PRIBITS_SHIFT); in icv_ctlr_read()
701 if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM) { in icv_ctlr_read()
705 if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR) { in icv_ctlr_read()
709 trace_gicv3_icv_ctlr_read(gicv3_redist_affid(cs), value); in icv_ctlr_read()
716 GICv3CPUState *cs = icc_cs_from_env(env); in icv_ctlr_write() local
718 trace_gicv3_icv_ctlr_write(gicv3_redist_affid(cs), value); in icv_ctlr_write()
720 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VCBPR_SHIFT, in icv_ctlr_write()
721 1, value & ICC_CTLR_EL1_CBPR ? 1 : 0); in icv_ctlr_write()
722 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VEOIM_SHIFT, in icv_ctlr_write()
723 1, value & ICC_CTLR_EL1_EOIMODE ? 1 : 0); in icv_ctlr_write()
725 gicv3_cpuif_virt_irq_fiq_update(cs); in icv_ctlr_write()
730 GICv3CPUState *cs = icc_cs_from_env(env); in icv_rpr_read() local
731 uint64_t prio = ich_highest_active_virt_prio(cs); in icv_rpr_read()
733 if (cs->ich_apr[GICV3_G1NS][0] & ICV_AP1R_EL1_NMI) { in icv_rpr_read()
737 trace_gicv3_icv_rpr_read(gicv3_redist_affid(cs), prio); in icv_rpr_read()
743 GICv3CPUState *cs = icc_cs_from_env(env); in icv_hppir_read() local
744 int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS; in icv_hppir_read()
745 int idx = hppvi_index(cs); in icv_hppir_read()
749 if (cs->hppvlpi.grp == grp) { in icv_hppir_read()
750 value = cs->hppvlpi.irq; in icv_hppir_read()
753 uint64_t lr = cs->ich_lr_el2[idx]; in icv_hppir_read()
761 trace_gicv3_icv_hppir_read(ri->crm == 8 ? 0 : 1, in icv_hppir_read()
762 gicv3_redist_affid(cs), value); in icv_hppir_read()
766 static void icv_activate_irq(GICv3CPUState *cs, int idx, int grp) in icv_activate_irq() argument
772 uint32_t mask = icv_gprio_mask(cs, grp); in icv_activate_irq()
773 int prio = ich_lr_prio(cs->ich_lr_el2[idx]) & mask; in icv_activate_irq()
774 bool nmi = cs->ich_lr_el2[idx] & ICH_LR_EL2_NMI; in icv_activate_irq()
775 int aprbit = prio >> (8 - cs->vprebits); in icv_activate_irq()
779 cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT; in icv_activate_irq()
780 cs->ich_lr_el2[idx] |= ICH_LR_EL2_STATE_ACTIVE_BIT; in icv_activate_irq()
783 cs->ich_apr[grp][regno] |= ICV_AP1R_EL1_NMI; in icv_activate_irq()
785 cs->ich_apr[grp][regno] |= (1U << regbit); in icv_activate_irq()
789 static void icv_activate_vlpi(GICv3CPUState *cs) in icv_activate_vlpi() argument
791 uint32_t mask = icv_gprio_mask(cs, cs->hppvlpi.grp); in icv_activate_vlpi()
792 int prio = cs->hppvlpi.prio & mask; in icv_activate_vlpi()
793 int aprbit = prio >> (8 - cs->vprebits); in icv_activate_vlpi()
797 cs->ich_apr[cs->hppvlpi.grp][regno] |= (1U << regbit); in icv_activate_vlpi()
798 gicv3_redist_vlpi_pending(cs, cs->hppvlpi.irq, 0); in icv_activate_vlpi()
803 GICv3CPUState *cs = icc_cs_from_env(env); in icv_iar_read() local
804 int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS; in icv_iar_read()
805 int idx = hppvi_index(cs); in icv_iar_read()
810 if (cs->hppvlpi.grp == grp && icv_hppvlpi_can_preempt(cs)) { in icv_iar_read()
811 intid = cs->hppvlpi.irq; in icv_iar_read()
812 icv_activate_vlpi(cs); in icv_iar_read()
815 uint64_t lr = cs->ich_lr_el2[idx]; in icv_iar_read()
817 bool nmi = env->cp15.sctlr_el[el] & SCTLR_NMI && lr & ICH_LR_EL2_NMI; in icv_iar_read()
819 if (thisgrp == grp && icv_hppi_can_preempt(cs, lr)) { in icv_iar_read()
823 icv_activate_irq(cs, idx, grp); in icv_iar_read()
829 cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT; in icv_iar_read()
837 trace_gicv3_icv_iar_read(ri->crm == 8 ? 0 : 1, in icv_iar_read()
838 gicv3_redist_affid(cs), intid); in icv_iar_read()
840 gicv3_cpuif_virt_update(cs); in icv_iar_read()
847 GICv3CPUState *cs = icc_cs_from_env(env); in icv_nmiar1_read() local
848 int idx = hppvi_index(cs); in icv_nmiar1_read()
852 uint64_t lr = cs->ich_lr_el2[idx]; in icv_nmiar1_read()
855 if ((thisgrp == GICV3_G1NS) && icv_hppi_can_preempt(cs, lr)) { in icv_nmiar1_read()
859 icv_activate_irq(cs, idx, GICV3_G1NS); in icv_nmiar1_read()
865 cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT; in icv_nmiar1_read()
874 trace_gicv3_icv_nmiar1_read(gicv3_redist_affid(cs), intid); in icv_nmiar1_read()
876 gicv3_cpuif_virt_update(cs); in icv_nmiar1_read()
881 static uint32_t icc_fullprio_mask(GICv3CPUState *cs) in icc_fullprio_mask() argument
889 return (~0U << (8 - cs->pribits)) & 0xff; in icc_fullprio_mask()
892 static inline int icc_min_bpr(GICv3CPUState *cs) in icc_min_bpr() argument
895 return 7 - cs->prebits; in icc_min_bpr()
898 static inline int icc_min_bpr_ns(GICv3CPUState *cs) in icc_min_bpr_ns() argument
900 return icc_min_bpr(cs) + 1; in icc_min_bpr_ns()
903 static inline int icc_num_aprs(GICv3CPUState *cs) in icc_num_aprs() argument
905 /* Return the number of APR registers (1, 2, or 4) */ in icc_num_aprs()
906 int aprmax = 1 << MAX(cs->prebits - 5, 0); in icc_num_aprs()
907 assert(aprmax <= ARRAY_SIZE(cs->icc_apr[0])); in icc_num_aprs()
911 static int icc_highest_active_prio(GICv3CPUState *cs) in icc_highest_active_prio() argument
918 if (cs->nmi_support) { in icc_highest_active_prio()
925 * prioritization of NMI vs non-NMI. in icc_highest_active_prio()
927 if (cs->icc_apr[GICV3_G1][0] & ICC_AP1R_EL1_NMI) { in icc_highest_active_prio()
930 if (cs->icc_apr[GICV3_G1NS][0] & ICC_AP1R_EL1_NMI) { in icc_highest_active_prio()
931 return (cs->gic->gicd_ctlr & GICD_CTLR_DS) ? 0 : 0x80; in icc_highest_active_prio()
935 for (i = 0; i < icc_num_aprs(cs); i++) { in icc_highest_active_prio()
936 uint32_t apr = cs->icc_apr[GICV3_G0][i] | in icc_highest_active_prio()
937 cs->icc_apr[GICV3_G1][i] | cs->icc_apr[GICV3_G1NS][i]; in icc_highest_active_prio()
942 return (i * 32 + ctz32(apr)) << (icc_min_bpr(cs) + 1); in icc_highest_active_prio()
948 static uint32_t icc_gprio_mask(GICv3CPUState *cs, int group) in icc_gprio_mask() argument
953 * a BPR of 0 means the group priority bits are [7:1]; in icc_gprio_mask()
954 * a BPR of 1 means they are [7:2], and so on down to in icc_gprio_mask()
957 * a BPR of 0 is impossible (the minimum value is 1) in icc_gprio_mask()
958 * a BPR of 1 means the group priority bits are [7:1]; in icc_gprio_mask()
969 if ((group == GICV3_G1 && cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR) || in icc_gprio_mask()
971 cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) { in icc_gprio_mask()
975 bpr = cs->icc_bpr[group] & 7; in icc_gprio_mask()
979 bpr--; in icc_gprio_mask()
982 return ~0U << (bpr + 1); in icc_gprio_mask()
985 static bool icc_no_enabled_hppi(GICv3CPUState *cs) in icc_no_enabled_hppi() argument
991 return cs->hppi.prio == 0xff || (cs->icc_igrpen[cs->hppi.grp] == 0); in icc_no_enabled_hppi()
994 static bool icc_hppi_can_preempt(GICv3CPUState *cs) in icc_hppi_can_preempt() argument
1001 ARMCPU *cpu = ARM_CPU(cs->cpu); in icc_hppi_can_preempt()
1002 CPUARMState *env = &cpu->env; in icc_hppi_can_preempt()
1004 if (icc_no_enabled_hppi(cs)) { in icc_hppi_can_preempt()
1008 if (cs->hppi.nmi) { in icc_hppi_can_preempt()
1009 if (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) && in icc_hppi_can_preempt()
1010 cs->hppi.grp == GICV3_G1NS) { in icc_hppi_can_preempt()
1011 if (cs->icc_pmr_el1 < 0x80) { in icc_hppi_can_preempt()
1014 if (arm_is_secure(env) && cs->icc_pmr_el1 == 0x80) { in icc_hppi_can_preempt()
1018 } else if (cs->hppi.prio >= cs->icc_pmr_el1) { in icc_hppi_can_preempt()
1023 rprio = icc_highest_active_prio(cs); in icc_hppi_can_preempt()
1029 mask = icc_gprio_mask(cs, cs->hppi.grp); in icc_hppi_can_preempt()
1034 if ((cs->hppi.prio & mask) < (rprio & mask)) { in icc_hppi_can_preempt()
1038 if (cs->hppi.nmi && (cs->hppi.prio & mask) == (rprio & mask)) { in icc_hppi_can_preempt()
1039 if (!(cs->icc_apr[cs->hppi.grp][0] & ICC_AP1R_EL1_NMI)) { in icc_hppi_can_preempt()
1047 void gicv3_cpuif_update(GICv3CPUState *cs) in gicv3_cpuif_update() argument
1053 ARMCPU *cpu = ARM_CPU(cs->cpu); in gicv3_cpuif_update()
1054 CPUARMState *env = &cpu->env; in gicv3_cpuif_update()
1058 trace_gicv3_cpuif_update(gicv3_redist_affid(cs), cs->hppi.irq, in gicv3_cpuif_update()
1059 cs->hppi.grp, cs->hppi.prio); in gicv3_cpuif_update()
1061 if (cs->hppi.grp == GICV3_G1 && !arm_feature(env, ARM_FEATURE_EL3)) { in gicv3_cpuif_update()
1062 /* If a Security-enabled GIC sends a G1S interrupt to a in gicv3_cpuif_update()
1063 * Security-disabled CPU, we must treat it as if it were G0. in gicv3_cpuif_update()
1065 cs->hppi.grp = GICV3_G0; in gicv3_cpuif_update()
1068 if (icc_hppi_can_preempt(cs)) { in gicv3_cpuif_update()
1074 switch (cs->hppi.grp) { in gicv3_cpuif_update()
1090 fiqlevel = 1; in gicv3_cpuif_update()
1091 } else if (cs->hppi.nmi) { in gicv3_cpuif_update()
1092 nmilevel = 1; in gicv3_cpuif_update()
1094 irqlevel = 1; in gicv3_cpuif_update()
1098 trace_gicv3_cpuif_set_irqs(gicv3_redist_affid(cs), fiqlevel, irqlevel); in gicv3_cpuif_update()
1100 qemu_set_irq(cs->parent_fiq, fiqlevel); in gicv3_cpuif_update()
1101 qemu_set_irq(cs->parent_irq, irqlevel); in gicv3_cpuif_update()
1102 qemu_set_irq(cs->parent_nmi, nmilevel); in gicv3_cpuif_update()
1107 GICv3CPUState *cs = icc_cs_from_env(env); in icc_pmr_read() local
1108 uint32_t value = cs->icc_pmr_el1; in icc_pmr_read()
1115 (env->cp15.scr_el3 & SCR_FIQ)) { in icc_pmr_read()
1123 value = (value << 1) & 0xff; in icc_pmr_read()
1127 trace_gicv3_icc_pmr_read(gicv3_redist_affid(cs), value); in icc_pmr_read()
1135 GICv3CPUState *cs = icc_cs_from_env(env); in icc_pmr_write() local
1141 trace_gicv3_icc_pmr_write(gicv3_redist_affid(cs), value); in icc_pmr_write()
1144 (env->cp15.scr_el3 & SCR_FIQ)) { in icc_pmr_write()
1148 if (!(cs->icc_pmr_el1 & 0x80)) { in icc_pmr_write()
1152 value = (value >> 1) | 0x80; in icc_pmr_write()
1154 value &= icc_fullprio_mask(cs); in icc_pmr_write()
1155 cs->icc_pmr_el1 = value; in icc_pmr_write()
1156 gicv3_cpuif_update(cs); in icc_pmr_write()
1159 static void icc_activate_irq(GICv3CPUState *cs, int irq) in icc_activate_irq() argument
1164 uint32_t mask = icc_gprio_mask(cs, cs->hppi.grp); in icc_activate_irq()
1165 int prio = cs->hppi.prio & mask; in icc_activate_irq()
1166 int aprbit = prio >> (8 - cs->prebits); in icc_activate_irq()
1169 bool nmi = cs->hppi.nmi; in icc_activate_irq()
1172 cs->icc_apr[cs->hppi.grp][regno] |= ICC_AP1R_EL1_NMI; in icc_activate_irq()
1174 cs->icc_apr[cs->hppi.grp][regno] |= (1U << regbit); in icc_activate_irq()
1178 cs->gicr_iactiver0 = deposit32(cs->gicr_iactiver0, irq, 1, 1); in icc_activate_irq()
1179 cs->gicr_ipendr0 = deposit32(cs->gicr_ipendr0, irq, 1, 0); in icc_activate_irq()
1180 gicv3_redist_update(cs); in icc_activate_irq()
1182 gicv3_gicd_active_set(cs->gic, irq); in icc_activate_irq()
1183 gicv3_gicd_pending_clear(cs->gic, irq); in icc_activate_irq()
1184 gicv3_update(cs->gic, irq, 1); in icc_activate_irq()
1186 gicv3_redist_lpi_pending(cs, irq, 0); in icc_activate_irq()
1190 static uint64_t icc_hppir0_value(GICv3CPUState *cs, CPUARMState *env) in icc_hppir0_value() argument
1197 if (icc_no_enabled_hppi(cs)) { in icc_hppir0_value()
1206 irq_is_secure = (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) && in icc_hppir0_value()
1207 (cs->hppi.grp != GICV3_G1NS)); in icc_hppir0_value()
1209 if (cs->hppi.grp != GICV3_G0 && !arm_is_el3_or_mon(env)) { in icc_hppir0_value()
1217 if (cs->hppi.grp != GICV3_G0) { in icc_hppir0_value()
1218 /* Indicate to EL3 that there's a Group 1 interrupt for the other in icc_hppir0_value()
1224 return cs->hppi.irq; in icc_hppir0_value()
1227 static uint64_t icc_hppir1_value(GICv3CPUState *cs, CPUARMState *env) in icc_hppir1_value() argument
1230 * for group 1. in icc_hppir1_value()
1234 if (icc_no_enabled_hppi(cs)) { in icc_hppir1_value()
1243 irq_is_secure = (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) && in icc_hppir1_value()
1244 (cs->hppi.grp != GICV3_G1NS)); in icc_hppir1_value()
1246 if (cs->hppi.grp == GICV3_G0) { in icc_hppir1_value()
1252 /* Secure interrupts not visible in Non-secure */ in icc_hppir1_value()
1256 /* Group 1 non-secure interrupts not visible in Secure EL1 */ in icc_hppir1_value()
1260 return cs->hppi.irq; in icc_hppir1_value()
1265 GICv3CPUState *cs = icc_cs_from_env(env); in icc_iar0_read() local
1272 if (!icc_hppi_can_preempt(cs)) { in icc_iar0_read()
1275 intid = icc_hppir0_value(cs, env); in icc_iar0_read()
1279 icc_activate_irq(cs, intid); in icc_iar0_read()
1282 trace_gicv3_icc_iar0_read(gicv3_redist_affid(cs), intid); in icc_iar0_read()
1288 GICv3CPUState *cs = icc_cs_from_env(env); in icc_iar1_read() local
1296 if (!icc_hppi_can_preempt(cs)) { in icc_iar1_read()
1299 intid = icc_hppir1_value(cs, env); in icc_iar1_read()
1303 if (cs->hppi.nmi && env->cp15.sctlr_el[el] & SCTLR_NMI) { in icc_iar1_read()
1306 icc_activate_irq(cs, intid); in icc_iar1_read()
1310 trace_gicv3_icc_iar1_read(gicv3_redist_affid(cs), intid); in icc_iar1_read()
1316 GICv3CPUState *cs = icc_cs_from_env(env); in icc_nmiar1_read() local
1323 if (!icc_hppi_can_preempt(cs)) { in icc_nmiar1_read()
1326 intid = icc_hppir1_value(cs, env); in icc_nmiar1_read()
1330 if (!cs->hppi.nmi) { in icc_nmiar1_read()
1333 icc_activate_irq(cs, intid); in icc_nmiar1_read()
1337 trace_gicv3_icc_nmiar1_read(gicv3_redist_affid(cs), intid); in icc_nmiar1_read()
1341 static void icc_drop_prio(GICv3CPUState *cs, int grp) in icc_drop_prio() argument
1361 for (i = 0; i < icc_num_aprs(cs); i++) { in icc_drop_prio()
1362 uint64_t *papr = &cs->icc_apr[grp][i]; in icc_drop_prio()
1368 if (i == 0 && cs->nmi_support && (*papr & ICC_AP1R_EL1_NMI)) { in icc_drop_prio()
1374 *papr &= *papr - 1; in icc_drop_prio()
1379 gicv3_cpuif_update(cs); in icc_drop_prio()
1382 static bool icc_eoi_split(CPUARMState *env, GICv3CPUState *cs) in icc_eoi_split() argument
1388 return cs->icc_ctlr_el3 & ICC_CTLR_EL3_EOIMODE_EL3; in icc_eoi_split()
1391 return cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1393 return cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1397 static int icc_highest_active_group(GICv3CPUState *cs) in icc_highest_active_group() argument
1407 if (cs->nmi_support) { in icc_highest_active_group()
1408 if (cs->icc_apr[GICV3_G1][0] & ICC_AP1R_EL1_NMI) { in icc_highest_active_group()
1411 if (cs->icc_apr[GICV3_G1NS][0] & ICC_AP1R_EL1_NMI) { in icc_highest_active_group()
1416 for (i = 0; i < ARRAY_SIZE(cs->icc_apr[0]); i++) { in icc_highest_active_group()
1417 int g0ctz = ctz32(cs->icc_apr[GICV3_G0][i]); in icc_highest_active_group()
1418 int g1ctz = ctz32(cs->icc_apr[GICV3_G1][i]); in icc_highest_active_group()
1419 int g1nsctz = ctz32(cs->icc_apr[GICV3_G1NS][i]); in icc_highest_active_group()
1431 /* No set active bits? UNPREDICTABLE; return -1 so the caller in icc_highest_active_group()
1434 return -1; in icc_highest_active_group()
1437 static void icc_deactivate_irq(GICv3CPUState *cs, int irq) in icc_deactivate_irq() argument
1440 cs->gicr_iactiver0 = deposit32(cs->gicr_iactiver0, irq, 1, 0); in icc_deactivate_irq()
1441 gicv3_redist_update(cs); in icc_deactivate_irq()
1443 gicv3_gicd_active_clear(cs->gic, irq); in icc_deactivate_irq()
1444 gicv3_update(cs->gic, irq, 1); in icc_deactivate_irq()
1448 static bool icv_eoi_split(CPUARMState *env, GICv3CPUState *cs) in icv_eoi_split() argument
1453 return cs->ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM; in icv_eoi_split()
1456 static int icv_find_active(GICv3CPUState *cs, int irq) in icv_find_active() argument
1459 * of the corresponding list register, or -1 if there is no match. in icv_find_active()
1464 for (i = 0; i < cs->num_list_regs; i++) { in icv_find_active()
1465 uint64_t lr = cs->ich_lr_el2[i]; in icv_find_active()
1472 return -1; in icv_find_active()
1475 static void icv_deactivate_irq(GICv3CPUState *cs, int idx) in icv_deactivate_irq() argument
1478 uint64_t lr = cs->ich_lr_el2[idx]; in icv_deactivate_irq()
1485 icc_deactivate_irq(cs, pirq); in icv_deactivate_irq()
1489 /* Clear the 'active' part of the state, so ActivePending->Pending in icv_deactivate_irq()
1490 * and Active->Invalid. in icv_deactivate_irq()
1493 cs->ich_lr_el2[idx] = lr; in icv_deactivate_irq()
1496 static void icv_increment_eoicount(GICv3CPUState *cs) in icv_increment_eoicount() argument
1499 int eoicount = extract64(cs->ich_hcr_el2, ICH_HCR_EL2_EOICOUNT_SHIFT, in icv_increment_eoicount()
1502 cs->ich_hcr_el2 = deposit64(cs->ich_hcr_el2, ICH_HCR_EL2_EOICOUNT_SHIFT, in icv_increment_eoicount()
1503 ICH_HCR_EL2_EOICOUNT_LENGTH, eoicount + 1); in icv_increment_eoicount()
1506 static int icv_drop_prio(GICv3CPUState *cs, bool *nmi) in icv_drop_prio() argument
1510 * the same priority for both group 0 and group 1). in icv_drop_prio()
1517 int aprmax = ich_num_aprs(cs); in icv_drop_prio()
1520 uint64_t *papr0 = &cs->ich_apr[GICV3_G0][i]; in icv_drop_prio()
1521 uint64_t *papr1 = &cs->ich_apr[GICV3_G1NS][i]; in icv_drop_prio()
1528 if (i == 0 && cs->nmi_support && (*papr1 & ICV_AP1R_EL1_NMI)) { in icv_drop_prio()
1534 /* We can't just use the bit-twiddling hack icc_drop_prio() does in icv_drop_prio()
1542 *papr0 &= *papr0 - 1; in icv_drop_prio()
1543 return (apr0count + i * 32) << (icv_min_vbpr(cs) + 1); in icv_drop_prio()
1545 *papr1 &= *papr1 - 1; in icv_drop_prio()
1546 return (apr1count + i * 32) << (icv_min_vbpr(cs) + 1); in icv_drop_prio()
1556 GICv3CPUState *cs = icc_cs_from_env(env); in icv_dir_write() local
1560 trace_gicv3_icv_dir_write(gicv3_redist_affid(cs), value); in icv_dir_write()
1567 if (!icv_eoi_split(env, cs)) { in icv_dir_write()
1571 idx = icv_find_active(cs, irq); in icv_dir_write()
1577 icv_increment_eoicount(cs); in icv_dir_write()
1579 icv_deactivate_irq(cs, idx); in icv_dir_write()
1582 gicv3_cpuif_virt_update(cs); in icv_dir_write()
1589 GICv3CPUState *cs = icc_cs_from_env(env); in icv_eoir_write() local
1591 int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS; in icv_eoir_write()
1595 trace_gicv3_icv_eoir_write(ri->crm == 8 ? 0 : 1, in icv_eoir_write()
1596 gicv3_redist_affid(cs), value); in icv_eoir_write()
1606 dropprio = icv_drop_prio(cs, &nmi); in icv_eoir_write()
1615 idx = icv_find_active(cs, irq); in icv_eoir_write()
1623 icv_increment_eoicount(cs); in icv_eoir_write()
1626 uint64_t lr = cs->ich_lr_el2[idx]; in icv_eoir_write()
1628 int lr_gprio = ich_lr_prio(lr) & icv_gprio_mask(cs, grp); in icv_eoir_write()
1632 if (!icv_eoi_split(env, cs) || irq >= GICV3_LPI_INTID_START) { in icv_eoir_write()
1638 icv_deactivate_irq(cs, idx); in icv_eoir_write()
1643 gicv3_cpuif_virt_update(cs); in icv_eoir_write()
1650 GICv3CPUState *cs = icc_cs_from_env(env); in icc_eoir_write() local
1653 bool is_eoir0 = ri->crm == 8; in icc_eoir_write()
1660 trace_gicv3_icc_eoir_write(is_eoir0 ? 0 : 1, in icc_eoir_write()
1661 gicv3_redist_affid(cs), value); in icc_eoir_write()
1663 if ((irq >= cs->gic->num_irq) && in icc_eoir_write()
1664 !(cs->gic->lpi_enable && (irq >= GICV3_LPI_INTID_START))) { in icc_eoir_write()
1666 * 1. If software writes the ID of a spurious interrupt [ie 1020-1023] in icc_eoir_write()
1668 * 2. If software writes the number of a non-existent interrupt in icc_eoir_write()
1676 grp = icc_highest_active_group(cs); in icc_eoir_write()
1682 if (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) in icc_eoir_write()
1709 icc_drop_prio(cs, grp); in icc_eoir_write()
1711 if (!icc_eoi_split(env, cs)) { in icc_eoir_write()
1713 icc_deactivate_irq(cs, irq); in icc_eoir_write()
1719 GICv3CPUState *cs = icc_cs_from_env(env); in icc_hppir0_read() local
1726 value = icc_hppir0_value(cs, env); in icc_hppir0_read()
1727 trace_gicv3_icc_hppir0_read(gicv3_redist_affid(cs), value); in icc_hppir0_read()
1733 GICv3CPUState *cs = icc_cs_from_env(env); in icc_hppir1_read() local
1740 value = icc_hppir1_value(cs, env); in icc_hppir1_read()
1741 trace_gicv3_icc_hppir1_read(gicv3_redist_affid(cs), value); in icc_hppir1_read()
1747 GICv3CPUState *cs = icc_cs_from_env(env); in icc_bpr_read() local
1748 int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1; in icc_bpr_read()
1761 (cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR)) { in icc_bpr_read()
1769 (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) { in icc_bpr_read()
1770 /* reads return bpr0 + 1 sat to 7, writes ignored */ in icc_bpr_read()
1775 bpr = cs->icc_bpr[grp]; in icc_bpr_read()
1781 trace_gicv3_icc_bpr_read(ri->crm == 8 ? 0 : 1, gicv3_redist_affid(cs), bpr); in icc_bpr_read()
1789 GICv3CPUState *cs = icc_cs_from_env(env); in icc_bpr_write() local
1790 int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1; in icc_bpr_write()
1798 trace_gicv3_icc_bpr_write(ri->crm == 8 ? 0 : 1, in icc_bpr_write()
1799 gicv3_redist_affid(cs), value); in icc_bpr_write()
1806 (cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR)) { in icc_bpr_write()
1814 (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) { in icc_bpr_write()
1815 /* reads return bpr0 + 1 sat to 7, writes ignored */ in icc_bpr_write()
1819 minval = (grp == GICV3_G1NS) ? icc_min_bpr_ns(cs) : icc_min_bpr(cs); in icc_bpr_write()
1824 cs->icc_bpr[grp] = value & 7; in icc_bpr_write()
1825 gicv3_cpuif_update(cs); in icc_bpr_write()
1830 GICv3CPUState *cs = icc_cs_from_env(env); in icc_ap_read() local
1833 int regno = ri->opc2 & 3; in icc_ap_read()
1834 int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0; in icc_ap_read()
1844 value = cs->icc_apr[grp][regno]; in icc_ap_read()
1846 trace_gicv3_icc_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value); in icc_ap_read()
1853 GICv3CPUState *cs = icc_cs_from_env(env); in icc_ap_write() local
1855 int regno = ri->opc2 & 3; in icc_ap_write()
1856 int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0; in icc_ap_write()
1863 trace_gicv3_icc_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); in icc_ap_write()
1869 /* It's not possible to claim that a Non-secure interrupt is active in icc_ap_write()
1870 * at a priority outside the Non-secure range (128..255), since this in icc_ap_write()
1878 if (cs->nmi_support) { in icc_ap_write()
1879 cs->icc_apr[grp][regno] = value & (0xFFFFFFFFU | ICC_AP1R_EL1_NMI); in icc_ap_write()
1881 cs->icc_apr[grp][regno] = value & 0xFFFFFFFFU; in icc_ap_write()
1883 gicv3_cpuif_update(cs); in icc_ap_write()
1890 GICv3CPUState *cs = icc_cs_from_env(env); in icc_dir_write() local
1900 trace_gicv3_icc_dir_write(gicv3_redist_affid(cs), value); in icc_dir_write()
1902 if (irq >= cs->gic->num_irq) { in icc_dir_write()
1907 if (!icc_eoi_split(env, cs)) { in icc_dir_write()
1911 int grp = gicv3_irq_group(cs->gic, cs, irq); in icc_dir_write()
1913 single_sec_state = cs->gic->gicd_ctlr & GICD_CTLR_DS; in icc_dir_write()
1921 route_fiq_to_el3 = env->cp15.scr_el3 & SCR_FIQ; in icc_dir_write()
1922 route_irq_to_el3 = env->cp15.scr_el3 & SCR_IRQ; in icc_dir_write()
1941 case 1: in icc_dir_write()
1966 icc_deactivate_irq(cs, irq); in icc_dir_write()
1971 GICv3CPUState *cs = icc_cs_from_env(env); in icc_rpr_read() local
1978 prio = icc_highest_active_prio(cs); in icc_rpr_read()
1981 !arm_is_secure(env) && (env->cp15.scr_el3 & SCR_FIQ)) { in icc_rpr_read()
1987 /* Non-idle priority: show the Non-secure view of it */ in icc_rpr_read()
1988 prio = (prio << 1) & 0xff; in icc_rpr_read()
1992 if (cs->nmi_support) { in icc_rpr_read()
1995 if (cs->icc_apr[GICV3_G1NS][0] & ICC_AP1R_EL1_NMI) { in icc_rpr_read()
1999 if (cs->icc_apr[GICV3_G1NS][0] & ICC_AP1R_EL1_NMI) { in icc_rpr_read()
2002 if (cs->icc_apr[GICV3_G1][0] & ICC_AP1R_EL1_NMI) { in icc_rpr_read()
2008 trace_gicv3_icc_rpr_read(gicv3_redist_affid(cs), prio); in icc_rpr_read()
2012 static void icc_generate_sgi(CPUARMState *env, GICv3CPUState *cs, in icc_generate_sgi() argument
2015 GICv3State *s = cs->gic; in icc_generate_sgi()
2023 bool irm = extract64(value, 40, 1); in icc_generate_sgi()
2026 if (grp == GICV3_G1 && s->gicd_ctlr & GICD_CTLR_DS) { in icc_generate_sgi()
2027 /* If GICD_CTLR.DS == 1, the Distributor treats Secure Group 1 in icc_generate_sgi()
2034 trace_gicv3_icc_generate_sgi(gicv3_redist_affid(cs), irq, irm, in icc_generate_sgi()
2037 for (i = 0; i < s->num_cpu; i++) { in icc_generate_sgi()
2038 GICv3CPUState *ocs = &s->cpu[i]; in icc_generate_sgi()
2041 /* IRM == 1 : route to all CPUs except self */ in icc_generate_sgi()
2042 if (cs == ocs) { in icc_generate_sgi()
2051 if (ocs->gicr_typer >> 40 != aff) { in icc_generate_sgi()
2054 aff0 = extract64(ocs->gicr_typer, 32, 8); in icc_generate_sgi()
2055 if (aff0 > 15 || extract32(targetlist, aff0, 1) == 0) { in icc_generate_sgi()
2069 GICv3CPUState *cs = icc_cs_from_env(env); in icc_sgi0r_write() local
2072 icc_generate_sgi(env, cs, value, GICV3_G0, ns); in icc_sgi0r_write()
2078 /* Generate Group 1 SGI for the current Security state */ in icc_sgi1r_write()
2079 GICv3CPUState *cs = icc_cs_from_env(env); in icc_sgi1r_write() local
2084 icc_generate_sgi(env, cs, value, grp, ns); in icc_sgi1r_write()
2090 /* Generate Group 1 SGI for the Security state that is not in icc_asgi1r_write()
2093 GICv3CPUState *cs = icc_cs_from_env(env); in icc_asgi1r_write() local
2098 icc_generate_sgi(env, cs, value, grp, ns); in icc_asgi1r_write()
2103 GICv3CPUState *cs = icc_cs_from_env(env); in icc_igrpen_read() local
2104 int grp = ri->opc2 & 1 ? GICV3_G1 : GICV3_G0; in icc_igrpen_read()
2115 value = cs->icc_igrpen[grp]; in icc_igrpen_read()
2116 trace_gicv3_icc_igrpen_read(ri->opc2 & 1 ? 1 : 0, in icc_igrpen_read()
2117 gicv3_redist_affid(cs), value); in icc_igrpen_read()
2124 GICv3CPUState *cs = icc_cs_from_env(env); in icc_igrpen_write() local
2125 int grp = ri->opc2 & 1 ? GICV3_G1 : GICV3_G0; in icc_igrpen_write()
2132 trace_gicv3_icc_igrpen_write(ri->opc2 & 1 ? 1 : 0, in icc_igrpen_write()
2133 gicv3_redist_affid(cs), value); in icc_igrpen_write()
2139 cs->icc_igrpen[grp] = value & ICC_IGRPEN_ENABLE; in icc_igrpen_write()
2140 gicv3_cpuif_update(cs); in icc_igrpen_write()
2145 GICv3CPUState *cs = icc_cs_from_env(env); in icc_igrpen1_el3_read() local
2148 /* IGRPEN1_EL3 bits 0 and 1 are r/w aliases into IGRPEN1_EL1 NS and S */ in icc_igrpen1_el3_read()
2149 value = cs->icc_igrpen[GICV3_G1NS] | (cs->icc_igrpen[GICV3_G1] << 1); in icc_igrpen1_el3_read()
2150 trace_gicv3_icc_igrpen1_el3_read(gicv3_redist_affid(cs), value); in icc_igrpen1_el3_read()
2157 GICv3CPUState *cs = icc_cs_from_env(env); in icc_igrpen1_el3_write() local
2159 trace_gicv3_icc_igrpen1_el3_write(gicv3_redist_affid(cs), value); in icc_igrpen1_el3_write()
2161 /* IGRPEN1_EL3 bits 0 and 1 are r/w aliases into IGRPEN1_EL1 NS and S */ in icc_igrpen1_el3_write()
2162 cs->icc_igrpen[GICV3_G1NS] = extract32(value, 0, 1); in icc_igrpen1_el3_write()
2163 cs->icc_igrpen[GICV3_G1] = extract32(value, 1, 1); in icc_igrpen1_el3_write()
2164 gicv3_cpuif_update(cs); in icc_igrpen1_el3_write()
2169 GICv3CPUState *cs = icc_cs_from_env(env); in icc_ctlr_el1_read() local
2177 value = cs->icc_ctlr_el1[bank]; in icc_ctlr_el1_read()
2178 trace_gicv3_icc_ctlr_read(gicv3_redist_affid(cs), value); in icc_ctlr_el1_read()
2185 GICv3CPUState *cs = icc_cs_from_env(env); in icc_ctlr_el1_write() local
2194 trace_gicv3_icc_ctlr_write(gicv3_redist_affid(cs), value); in icc_ctlr_el1_write()
2197 * for us PMHE is RAZ/WI (we don't implement 1-of-N interrupts or in icc_ctlr_el1_write()
2198 * the asseciated priority-based routing of them); in icc_ctlr_el1_write()
2202 ((cs->gic->gicd_ctlr & GICD_CTLR_DS) == 0)) { in icc_ctlr_el1_write()
2208 cs->icc_ctlr_el1[bank] &= ~mask; in icc_ctlr_el1_write()
2209 cs->icc_ctlr_el1[bank] |= (value & mask); in icc_ctlr_el1_write()
2210 gicv3_cpuif_update(cs); in icc_ctlr_el1_write()
2216 GICv3CPUState *cs = icc_cs_from_env(env); in icc_ctlr_el3_read() local
2219 value = cs->icc_ctlr_el3; in icc_ctlr_el3_read()
2220 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
2223 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR) { in icc_ctlr_el3_read()
2226 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
2229 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR) { in icc_ctlr_el3_read()
2233 trace_gicv3_icc_ctlr_el3_read(gicv3_redist_affid(cs), value); in icc_ctlr_el3_read()
2240 GICv3CPUState *cs = icc_cs_from_env(env); in icc_ctlr_el3_write() local
2243 trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value); in icc_ctlr_el3_write()
2246 cs->icc_ctlr_el1[GICV3_NS] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); in icc_ctlr_el3_write()
2248 cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el3_write()
2251 cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR; in icc_ctlr_el3_write()
2254 cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); in icc_ctlr_el3_write()
2256 cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el3_write()
2259 cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_CBPR; in icc_ctlr_el3_write()
2265 cs->icc_ctlr_el3 &= ~mask; in icc_ctlr_el3_write()
2266 cs->icc_ctlr_el3 |= (value & mask); in icc_ctlr_el3_write()
2267 gicv3_cpuif_update(cs); in icc_ctlr_el3_write()
2274 GICv3CPUState *cs = icc_cs_from_env(env); in gicv3_irqfiq_access() local
2277 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_TC) && in gicv3_irqfiq_access()
2278 el == 1 && !arm_is_secure_below_el3(env)) { in gicv3_irqfiq_access()
2283 if ((env->cp15.scr_el3 & (SCR_FIQ | SCR_IRQ)) == (SCR_FIQ | SCR_IRQ)) { in gicv3_irqfiq_access()
2285 case 1: in gicv3_irqfiq_access()
2310 GICv3CPUState *cs = icc_cs_from_env(env); in gicv3_dir_access() local
2312 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_TDIR) && in gicv3_dir_access()
2313 arm_current_el(env) == 1 && !arm_is_secure_below_el3(env)) { in gicv3_dir_access()
2324 if (arm_current_el(env) == 1 && in gicv3_sgi_access()
2337 GICv3CPUState *cs = icc_cs_from_env(env); in gicv3_fiq_access() local
2340 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_TALL0) && in gicv3_fiq_access()
2341 el == 1 && !arm_is_secure_below_el3(env)) { in gicv3_fiq_access()
2346 if (env->cp15.scr_el3 & SCR_FIQ) { in gicv3_fiq_access()
2348 case 1: in gicv3_fiq_access()
2373 GICv3CPUState *cs = icc_cs_from_env(env); in gicv3_irq_access() local
2376 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_TALL1) && in gicv3_irq_access()
2377 el == 1 && !arm_is_secure_below_el3(env)) { in gicv3_irq_access()
2382 if (env->cp15.scr_el3 & SCR_IRQ) { in gicv3_irq_access()
2384 case 1: in gicv3_irq_access()
2407 GICv3CPUState *cs = icc_cs_from_env(env); in icc_reset() local
2409 cs->icc_ctlr_el1[GICV3_S] = ICC_CTLR_EL1_A3V | in icc_reset()
2410 (1 << ICC_CTLR_EL1_IDBITS_SHIFT) | in icc_reset()
2411 ((cs->pribits - 1) << ICC_CTLR_EL1_PRIBITS_SHIFT); in icc_reset()
2412 cs->icc_ctlr_el1[GICV3_NS] = ICC_CTLR_EL1_A3V | in icc_reset()
2413 (1 << ICC_CTLR_EL1_IDBITS_SHIFT) | in icc_reset()
2414 ((cs->pribits - 1) << ICC_CTLR_EL1_PRIBITS_SHIFT); in icc_reset()
2415 cs->icc_pmr_el1 = 0; in icc_reset()
2416 cs->icc_bpr[GICV3_G0] = icc_min_bpr(cs); in icc_reset()
2417 cs->icc_bpr[GICV3_G1] = icc_min_bpr(cs); in icc_reset()
2418 cs->icc_bpr[GICV3_G1NS] = icc_min_bpr_ns(cs); in icc_reset()
2419 memset(cs->icc_apr, 0, sizeof(cs->icc_apr)); in icc_reset()
2420 memset(cs->icc_igrpen, 0, sizeof(cs->icc_igrpen)); in icc_reset()
2421 cs->icc_ctlr_el3 = ICC_CTLR_EL3_NDS | ICC_CTLR_EL3_A3V | in icc_reset()
2422 (1 << ICC_CTLR_EL3_IDBITS_SHIFT) | in icc_reset()
2423 ((cs->pribits - 1) << ICC_CTLR_EL3_PRIBITS_SHIFT); in icc_reset()
2425 memset(cs->ich_apr, 0, sizeof(cs->ich_apr)); in icc_reset()
2426 cs->ich_hcr_el2 = 0; in icc_reset()
2427 memset(cs->ich_lr_el2, 0, sizeof(cs->ich_lr_el2)); in icc_reset()
2428 cs->ich_vmcr_el2 = ICH_VMCR_EL2_VFIQEN | in icc_reset()
2429 ((icv_min_vbpr(cs) + 1) << ICH_VMCR_EL2_VBPR1_SHIFT) | in icc_reset()
2430 (icv_min_vbpr(cs) << ICH_VMCR_EL2_VBPR0_SHIFT); in icc_reset()
2453 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 1,
2487 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 1,
2517 .cp = 15, .opc1 = 1, .crm = 12,
2541 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 1,
2639 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 1,
2689 GICv3CPUState *cs = icc_cs_from_env(env); in ich_ap_read() local
2690 int regno = ri->opc2 & 3; in ich_ap_read()
2691 int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; in ich_ap_read()
2694 value = cs->ich_apr[grp][regno]; in ich_ap_read()
2695 trace_gicv3_ich_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value); in ich_ap_read()
2702 GICv3CPUState *cs = icc_cs_from_env(env); in ich_ap_write() local
2703 int regno = ri->opc2 & 3; in ich_ap_write()
2704 int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; in ich_ap_write()
2706 trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); in ich_ap_write()
2708 if (cs->nmi_support) { in ich_ap_write()
2709 cs->ich_apr[grp][regno] = value & (0xFFFFFFFFU | ICV_AP1R_EL1_NMI); in ich_ap_write()
2711 cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU; in ich_ap_write()
2713 gicv3_cpuif_virt_irq_fiq_update(cs); in ich_ap_write()
2718 GICv3CPUState *cs = icc_cs_from_env(env); in ich_hcr_read() local
2719 uint64_t value = cs->ich_hcr_el2; in ich_hcr_read()
2721 trace_gicv3_ich_hcr_read(gicv3_redist_affid(cs), value); in ich_hcr_read()
2728 GICv3CPUState *cs = icc_cs_from_env(env); in ich_hcr_write() local
2730 trace_gicv3_ich_hcr_write(gicv3_redist_affid(cs), value); in ich_hcr_write()
2738 cs->ich_hcr_el2 = value; in ich_hcr_write()
2739 gicv3_cpuif_virt_update(cs); in ich_hcr_write()
2744 GICv3CPUState *cs = icc_cs_from_env(env); in ich_vmcr_read() local
2745 uint64_t value = cs->ich_vmcr_el2; in ich_vmcr_read()
2747 trace_gicv3_ich_vmcr_read(gicv3_redist_affid(cs), value); in ich_vmcr_read()
2754 GICv3CPUState *cs = icc_cs_from_env(env); in ich_vmcr_write() local
2756 trace_gicv3_ich_vmcr_write(gicv3_redist_affid(cs), value); in ich_vmcr_write()
2763 cs->ich_vmcr_el2 = value; in ich_vmcr_write()
2767 write_vbpr(cs, GICV3_G0, read_vbpr(cs, GICV3_G0)); in ich_vmcr_write()
2768 write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G1)); in ich_vmcr_write()
2770 gicv3_cpuif_virt_update(cs); in ich_vmcr_write()
2775 GICv3CPUState *cs = icc_cs_from_env(env); in ich_lr_read() local
2776 int regno = ri->opc2 | ((ri->crm & 1) << 3); in ich_lr_read()
2780 * 64-bit reads of the whole LR in ich_lr_read()
2781 * 32-bit reads of the low half of the LR in ich_lr_read()
2782 * 32-bit reads of the high half of the LR in ich_lr_read()
2784 if (ri->state == ARM_CP_STATE_AA32) { in ich_lr_read()
2785 if (ri->crm >= 14) { in ich_lr_read()
2786 value = extract64(cs->ich_lr_el2[regno], 32, 32); in ich_lr_read()
2787 trace_gicv3_ich_lrc_read(regno, gicv3_redist_affid(cs), value); in ich_lr_read()
2789 value = extract64(cs->ich_lr_el2[regno], 0, 32); in ich_lr_read()
2790 trace_gicv3_ich_lr32_read(regno, gicv3_redist_affid(cs), value); in ich_lr_read()
2793 value = cs->ich_lr_el2[regno]; in ich_lr_read()
2794 trace_gicv3_ich_lr_read(regno, gicv3_redist_affid(cs), value); in ich_lr_read()
2803 GICv3CPUState *cs = icc_cs_from_env(env); in ich_lr_write() local
2804 int regno = ri->opc2 | ((ri->crm & 1) << 3); in ich_lr_write()
2807 * 64-bit writes to the whole LR in ich_lr_write()
2808 * 32-bit writes to the low half of the LR in ich_lr_write()
2809 * 32-bit writes to the high half of the LR in ich_lr_write()
2811 if (ri->state == ARM_CP_STATE_AA32) { in ich_lr_write()
2812 if (ri->crm >= 14) { in ich_lr_write()
2813 trace_gicv3_ich_lrc_write(regno, gicv3_redist_affid(cs), value); in ich_lr_write()
2814 value = deposit64(cs->ich_lr_el2[regno], 32, 32, value); in ich_lr_write()
2816 trace_gicv3_ich_lr32_write(regno, gicv3_redist_affid(cs), value); in ich_lr_write()
2817 value = deposit64(cs->ich_lr_el2[regno], 0, 32, value); in ich_lr_write()
2820 trace_gicv3_ich_lr_write(regno, gicv3_redist_affid(cs), value); in ich_lr_write()
2824 if (cs->vpribits < 8) { in ich_lr_write()
2826 8 - cs->vpribits, 0); in ich_lr_write()
2830 if (!cs->nmi_support) { in ich_lr_write()
2834 cs->ich_lr_el2[regno] = value; in ich_lr_write()
2835 gicv3_cpuif_virt_update(cs); in ich_lr_write()
2840 GICv3CPUState *cs = icc_cs_from_env(env); in ich_vtr_read() local
2843 value = ((cs->num_list_regs - 1) << ICH_VTR_EL2_LISTREGS_SHIFT) in ich_vtr_read()
2845 | (1 << ICH_VTR_EL2_IDBITS_SHIFT) in ich_vtr_read()
2846 | ((cs->vprebits - 1) << ICH_VTR_EL2_PREBITS_SHIFT) in ich_vtr_read()
2847 | ((cs->vpribits - 1) << ICH_VTR_EL2_PRIBITS_SHIFT); in ich_vtr_read()
2849 if (cs->gic->revision < 4) { in ich_vtr_read()
2853 trace_gicv3_ich_vtr_read(gicv3_redist_affid(cs), value); in ich_vtr_read()
2859 GICv3CPUState *cs = icc_cs_from_env(env); in ich_misr_read() local
2860 uint64_t value = maintenance_interrupt_state(cs); in ich_misr_read()
2862 trace_gicv3_ich_misr_read(gicv3_redist_affid(cs), value); in ich_misr_read()
2868 GICv3CPUState *cs = icc_cs_from_env(env); in ich_eisr_read() local
2869 uint64_t value = eoi_maintenance_interrupt_state(cs, NULL); in ich_eisr_read()
2871 trace_gicv3_ich_eisr_read(gicv3_redist_affid(cs), value); in ich_eisr_read()
2877 GICv3CPUState *cs = icc_cs_from_env(env); in ich_elrsr_read() local
2881 for (i = 0; i < cs->num_list_regs; i++) { in ich_elrsr_read()
2882 uint64_t lr = cs->ich_lr_el2[i]; in ich_elrsr_read()
2886 value |= (1 << i); in ich_elrsr_read()
2890 trace_gicv3_ich_elrsr_read(gicv3_redist_affid(cs), value); in ich_elrsr_read()
2920 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 1,
2955 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 8, .opc2 = 1,
2963 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 1,
3009 GICv3CPUState *cs = opaque; in gicv3_cpuif_el_change_hook() local
3011 gicv3_cpuif_update(cs); in gicv3_cpuif_el_change_hook()
3017 gicv3_cpuif_virt_irq_fiq_update(cs); in gicv3_cpuif_el_change_hook()
3027 for (i = 0; i < s->num_cpu; i++) { in gicv3_init_cpuif()
3029 GICv3CPUState *cs = &s->cpu[i]; in gicv3_init_cpuif() local
3035 * cpu->gic_num_lrs in gicv3_init_cpuif()
3036 * cpu->gic_vpribits in gicv3_init_cpuif()
3037 * cpu->gic_vprebits in gicv3_init_cpuif()
3038 * cpu->gic_pribits in gicv3_init_cpuif()
3043 * it might be with code translated by CPU 0 but run by CPU 1, in in gicv3_init_cpuif()
3045 * So instead we define the regs with no ri->opaque info, and in gicv3_init_cpuif()
3057 * that is a property of the GIC device in s->nmi_support; in gicv3_init_cpuif()
3058 * cs->nmi_support indicates the CPU interface's support. in gicv3_init_cpuif()
3061 cs->nmi_support = true; in gicv3_init_cpuif()
3071 if (s->force_8bit_prio) { in gicv3_init_cpuif()
3072 cs->pribits = 8; in gicv3_init_cpuif()
3074 cs->pribits = cpu->gic_pribits ?: 5; in gicv3_init_cpuif()
3087 cs->prebits = cs->pribits; in gicv3_init_cpuif()
3088 if (cs->prebits == 8) { in gicv3_init_cpuif()
3089 cs->prebits--; in gicv3_init_cpuif()
3095 g_assert(cs->pribits >= 4 && cs->pribits <= 8); in gicv3_init_cpuif()
3099 * for ICC_AP*R{1,2,3}_EL1 if the prebits value requires them. in gicv3_init_cpuif()
3101 if (cs->prebits >= 6) { in gicv3_init_cpuif()
3104 if (cs->prebits == 7) { in gicv3_init_cpuif()
3108 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { in gicv3_init_cpuif()
3111 cs->num_list_regs = cpu->gic_num_lrs ?: 4; in gicv3_init_cpuif()
3112 cs->vpribits = cpu->gic_vpribits ?: 5; in gicv3_init_cpuif()
3113 cs->vprebits = cpu->gic_vprebits ?: 5; in gicv3_init_cpuif()
3119 g_assert(cs->vprebits <= cs->vpribits); in gicv3_init_cpuif()
3120 g_assert(cs->vprebits >= 5 && cs->vprebits <= 7); in gicv3_init_cpuif()
3121 g_assert(cs->vpribits >= 5 && cs->vpribits <= 8); in gicv3_init_cpuif()
3125 for (j = 0; j < cs->num_list_regs; j++) { in gicv3_init_cpuif()
3126 /* Note that the AArch64 LRs are 64-bit; the AArch32 LRs in gicv3_init_cpuif()
3151 if (cs->vprebits >= 6) { in gicv3_init_cpuif()
3154 if (cs->vprebits == 7) { in gicv3_init_cpuif()
3162 * the non-TCG case this is OK, as EL2 and EL3 can't exist. in gicv3_init_cpuif()
3164 arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, cs); in gicv3_init_cpuif()
3166 assert(!arm_feature(&cpu->env, ARM_FEATURE_EL2)); in gicv3_init_cpuif()
3167 assert(!arm_feature(&cpu->env, ARM_FEATURE_EL3)); in gicv3_init_cpuif()