Lines Matching full:aic
40 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); in aspeed_i2c_bus_raise_interrupt() local
77 qemu_irq_raise(aic->bus_get_irq(bus)); in aspeed_i2c_bus_raise_interrupt()
83 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); in aspeed_i2c_bus_raise_slave_interrupt() local
90 qemu_irq_raise(aic->bus_get_irq(bus)); in aspeed_i2c_bus_raise_slave_interrupt()
96 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); in aspeed_i2c_bus_old_read() local
114 if (!aic->has_dma) { in aspeed_i2c_bus_old_read()
123 if (!aic->has_dma) { in aspeed_i2c_bus_old_read()
143 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); in aspeed_i2c_bus_new_read() local
178 if (!aic->has_dma64) { in aspeed_i2c_bus_new_read()
246 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); in aspeed_i2c_bus_send() local
258 uint8_t *pool_base = aic->bus_pool_base(bus); in aspeed_i2c_bus_send()
302 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); in aspeed_i2c_bus_recv() local
313 uint8_t *pool_base = aic->bus_pool_base(bus); in aspeed_i2c_bus_recv()
385 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); in aspeed_i2c_get_addr() local
394 uint8_t *pool_base = aic->bus_pool_base(bus); in aspeed_i2c_get_addr()
410 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); in aspeed_i2c_check_sram() local
416 if (!aic->check_sram) { in aspeed_i2c_check_sram()
567 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); in aspeed_i2c_bus_new_write() local
601 qemu_irq_lower(aic->bus_get_irq(bus)); in aspeed_i2c_bus_new_write()
609 qemu_irq_lower(aic->bus_get_irq(bus)); in aspeed_i2c_bus_new_write()
630 if (!aic->has_dma && in aspeed_i2c_bus_new_write()
734 qemu_irq_lower(aic->bus_get_irq(bus)); in aspeed_i2c_bus_new_write()
755 if (!aic->has_dma64) { in aspeed_i2c_bus_new_write()
767 if (!aic->has_dma64) { in aspeed_i2c_bus_new_write()
784 if (!aic->has_dma64) { in aspeed_i2c_bus_new_write()
804 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); in aspeed_i2c_bus_old_write() local
831 qemu_irq_lower(aic->bus_get_irq(bus)); in aspeed_i2c_bus_old_write()
866 if (!aic->has_dma && in aspeed_i2c_bus_old_write()
880 if (!aic->has_dma) { in aspeed_i2c_bus_old_write()
890 if (!aic->has_dma) { in aspeed_i2c_bus_old_write()
1088 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); in aspeed_i2c_instance_init() local
1091 for (i = 0; i < aic->num_busses; i++) { in aspeed_i2c_instance_init()
1207 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); in aspeed_i2c_realize() local
1208 uint32_t reg_offset = aic->reg_size + aic->reg_gap_size; in aspeed_i2c_realize()
1209 uint32_t pool_offset = aic->pool_size + aic->pool_gap_size; in aspeed_i2c_realize()
1213 "aspeed.i2c", aic->mem_size); in aspeed_i2c_realize()
1216 for (i = 0; i < aic->num_busses; i++) { in aspeed_i2c_realize()
1218 int offset = i < aic->gap ? 1 : 5; in aspeed_i2c_realize()
1236 if (aic->has_share_pool) { in aspeed_i2c_realize()
1239 "aspeed.i2c-share-pool", aic->pool_size); in aspeed_i2c_realize()
1240 memory_region_add_subregion(&s->iomem, aic->pool_base, in aspeed_i2c_realize()
1243 for (i = 0; i < aic->num_busses; i++) { in aspeed_i2c_realize()
1245 aic->pool_base + (pool_offset * i), in aspeed_i2c_realize()
1250 if (aic->has_dma) { in aspeed_i2c_realize()
1423 AspeedI2CClass *aic; in aspeed_i2c_bus_realize() local
1432 aic = ASPEED_I2C_GET_CLASS(s->controller); in aspeed_i2c_bus_realize()
1441 s, name, aic->reg_size); in aspeed_i2c_bus_realize()
1445 s, pool_name, aic->pool_size); in aspeed_i2c_bus_realize()
1491 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); in aspeed_2400_i2c_class_init() local
1495 aic->num_busses = 14; in aspeed_2400_i2c_class_init()
1496 aic->reg_size = 0x40; in aspeed_2400_i2c_class_init()
1497 aic->gap = 7; in aspeed_2400_i2c_class_init()
1498 aic->bus_get_irq = aspeed_2400_i2c_bus_get_irq; in aspeed_2400_i2c_class_init()
1499 aic->has_share_pool = true; in aspeed_2400_i2c_class_init()
1500 aic->pool_size = 0x800; in aspeed_2400_i2c_class_init()
1501 aic->pool_base = 0x800; in aspeed_2400_i2c_class_init()
1502 aic->bus_pool_base = aspeed_2400_i2c_bus_pool_base; in aspeed_2400_i2c_class_init()
1503 aic->mem_size = 0x1000; in aspeed_2400_i2c_class_init()
1525 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); in aspeed_2500_i2c_class_init() local
1529 aic->num_busses = 14; in aspeed_2500_i2c_class_init()
1530 aic->reg_size = 0x40; in aspeed_2500_i2c_class_init()
1531 aic->gap = 7; in aspeed_2500_i2c_class_init()
1532 aic->bus_get_irq = aspeed_2500_i2c_bus_get_irq; in aspeed_2500_i2c_class_init()
1533 aic->pool_size = 0x10; in aspeed_2500_i2c_class_init()
1534 aic->pool_base = 0x200; in aspeed_2500_i2c_class_init()
1535 aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base; in aspeed_2500_i2c_class_init()
1536 aic->check_sram = true; in aspeed_2500_i2c_class_init()
1537 aic->has_dma = true; in aspeed_2500_i2c_class_init()
1538 aic->mem_size = 0x1000; in aspeed_2500_i2c_class_init()
1555 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); in aspeed_2600_i2c_class_init() local
1559 aic->num_busses = 16; in aspeed_2600_i2c_class_init()
1560 aic->reg_size = 0x80; in aspeed_2600_i2c_class_init()
1561 aic->gap = -1; /* no gap */ in aspeed_2600_i2c_class_init()
1562 aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq; in aspeed_2600_i2c_class_init()
1563 aic->pool_size = 0x20; in aspeed_2600_i2c_class_init()
1564 aic->pool_base = 0xC00; in aspeed_2600_i2c_class_init()
1565 aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base; in aspeed_2600_i2c_class_init()
1566 aic->has_dma = true; in aspeed_2600_i2c_class_init()
1567 aic->mem_size = 0x1000; in aspeed_2600_i2c_class_init()
1579 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); in aspeed_1030_i2c_class_init() local
1583 aic->num_busses = 14; in aspeed_1030_i2c_class_init()
1584 aic->reg_size = 0x80; in aspeed_1030_i2c_class_init()
1585 aic->gap = -1; /* no gap */ in aspeed_1030_i2c_class_init()
1586 aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq; in aspeed_1030_i2c_class_init()
1587 aic->pool_size = 0x20; in aspeed_1030_i2c_class_init()
1588 aic->pool_base = 0xC00; in aspeed_1030_i2c_class_init()
1589 aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base; in aspeed_1030_i2c_class_init()
1590 aic->has_dma = true; in aspeed_1030_i2c_class_init()
1591 aic->mem_size = 0x10000; in aspeed_1030_i2c_class_init()
1603 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); in aspeed_2700_i2c_class_init() local
1607 aic->num_busses = 16; in aspeed_2700_i2c_class_init()
1608 aic->reg_size = 0x80; in aspeed_2700_i2c_class_init()
1609 aic->reg_gap_size = 0x80; in aspeed_2700_i2c_class_init()
1610 aic->gap = -1; /* no gap */ in aspeed_2700_i2c_class_init()
1611 aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq; in aspeed_2700_i2c_class_init()
1612 aic->pool_size = 0x20; in aspeed_2700_i2c_class_init()
1613 aic->pool_gap_size = 0xe0; in aspeed_2700_i2c_class_init()
1614 aic->pool_base = 0x1a0; in aspeed_2700_i2c_class_init()
1615 aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base; in aspeed_2700_i2c_class_init()
1616 aic->has_dma = true; in aspeed_2700_i2c_class_init()
1617 aic->mem_size = 0x2000; in aspeed_2700_i2c_class_init()
1618 aic->has_dma64 = true; in aspeed_2700_i2c_class_init()
1644 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); in type_init() local
1647 if (busnr >= 0 && busnr < aic->num_busses) { in type_init()