356 	u32 config_reg, baud_rate_val = 0;  in zynqmp_qspi_init_hw()  local
379 	config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);  in zynqmp_qspi_init_hw()
380 	config_reg &= ~GQSPI_CFG_MODE_EN_MASK;  in zynqmp_qspi_init_hw()
382 	config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;  in zynqmp_qspi_init_hw()
384 	config_reg &= ~GQSPI_CFG_ENDIAN_MASK;  in zynqmp_qspi_init_hw()
386 	config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;  in zynqmp_qspi_init_hw()
388 	config_reg |= GQSPI_CFG_WP_HOLD_MASK;  in zynqmp_qspi_init_hw()
390 	config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;  in zynqmp_qspi_init_hw()
393 		config_reg |= GQSPI_CFG_CLK_PHA_MASK;  in zynqmp_qspi_init_hw()
395 		config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;  in zynqmp_qspi_init_hw()
398 		config_reg |= GQSPI_CFG_CLK_POL_MASK;  in zynqmp_qspi_init_hw()
400 		config_reg &= ~GQSPI_CFG_CLK_POL_MASK;  in zynqmp_qspi_init_hw()
409 	config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;  in zynqmp_qspi_init_hw()
410 	config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);  in zynqmp_qspi_init_hw()
412 	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);  in zynqmp_qspi_init_hw()
559 	u32 config_reg, req_speed_hz, baud_rate_val = 0;  in zynqmp_qspi_config_op()  local
576 		config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);  in zynqmp_qspi_config_op()
578 		config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;  in zynqmp_qspi_config_op()
579 		config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);  in zynqmp_qspi_config_op()
580 		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);  in zynqmp_qspi_config_op()
747 	u32 config_reg, genfifoentry;  in zynqmp_process_dma_irq()  local
761 		config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);  in zynqmp_process_dma_irq()
762 		config_reg &= ~GQSPI_CFG_MODE_EN_MASK;  in zynqmp_process_dma_irq()
763 		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);  in zynqmp_process_dma_irq()
848 	u32 rx_bytes, rx_rem, config_reg;  in zynqmp_qspi_setuprxdma()  local
855 		config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);  in zynqmp_qspi_setuprxdma()
856 		config_reg &= ~GQSPI_CFG_MODE_EN_MASK;  in zynqmp_qspi_setuprxdma()
857 		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);  in zynqmp_qspi_setuprxdma()
882 	config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);  in zynqmp_qspi_setuprxdma()
883 	config_reg &= ~GQSPI_CFG_MODE_EN_MASK;  in zynqmp_qspi_setuprxdma()
884 	config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;  in zynqmp_qspi_setuprxdma()
885 	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);  in zynqmp_qspi_setuprxdma()
908 	u32 config_reg;  in zynqmp_qspi_write_op()  local
913 		config_reg = zynqmp_gqspi_read(xqspi,  in zynqmp_qspi_write_op()
915 		config_reg &= ~GQSPI_CFG_MODE_EN_MASK;  in zynqmp_qspi_write_op()
917 				   config_reg);  in zynqmp_qspi_write_op()