Lines Matching +full:0 +full:x01880000
11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
26 <0x01 0x00000000 0x00 0x2000>, /* GICC */
27 <0x01 0x00010000 0x00 0x1000>, /* GICH */
28 <0x01 0x00020000 0x00 0x2000>; /* GICV */
37 reg = <0x00 0x01820000 0x00 0x10000>;
38 socionext,synquacer-pre-its = <0x1000000 0x400000>;
46 reg = <0x00 0x00100000 0x00 0x20000>;
49 ranges = <0x0 0x00 0x00100000 0x20000>;
53 reg = <0x4044 0x8>;
59 reg = <0x4130 0x4>;
65 reg = <0x82e0 0x4>;
66 clocks = <&k3_clks 157 0>;
67 assigned-clocks = <&k3_clks 157 0>;
69 #clock-cells = <0>;
74 reg = <0x82e4 0x4>;
78 #clock-cells = <0>;
87 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
95 reg = <0x00 0x4d000000 0x00 0x80000>,
96 <0x00 0x4a600000 0x00 0x80000>,
97 <0x00 0x4a400000 0x00 0x80000>;
104 reg = <0x00 0x48000000 0x00 0x100000>;
105 #interrupt-cells = <0>;
117 reg = <0x00 0x485c0100 0x00 0x100>,
118 <0x00 0x4c000000 0x00 0x20000>,
119 <0x00 0x4a820000 0x00 0x20000>,
120 <0x00 0x4aa40000 0x00 0x20000>,
121 <0x00 0x4bc00000 0x00 0x100000>;
128 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
129 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
130 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
135 reg = <0x00 0x485c0000 0x00 0x100>,
136 <0x00 0x4a800000 0x00 0x20000>,
137 <0x00 0x4aa00000 0x00 0x40000>,
138 <0x00 0x4b800000 0x00 0x400000>;
145 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
146 <0x24>, /* CPSW_TX_CHAN */
147 <0x25>, /* SAUL_TX_0_CHAN */
148 <0x26>; /* SAUL_TX_1_CHAN */
149 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
150 <0x11>, /* RING_CPSW_TX_CHAN */
151 <0x12>, /* RING_SAUL_TX_0_CHAN */
152 <0x13>; /* RING_SAUL_TX_1_CHAN */
153 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
154 <0x2b>, /* CPSW_RX_CHAN */
155 <0x2d>, /* SAUL_RX_0_CHAN */
156 <0x2f>, /* SAUL_RX_1_CHAN */
157 <0x31>, /* SAUL_RX_2_CHAN */
158 <0x33>; /* SAUL_RX_3_CHAN */
159 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
160 <0x2c>, /* FLOW_CPSW_RX_CHAN */
161 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
162 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
173 reg = <0x00 0x44043000 0x00 0xfe0>;
193 reg = <0x00 0x40900000 0x00 0x1200>;
196 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
198 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
199 <&main_pktdma 0x7507 0>;
207 reg = <0x00 0x43600000 0x00 0x10000>,
208 <0x00 0x44880000 0x00 0x20000>,
209 <0x00 0x44860000 0x00 0x20000>;
220 reg = <0x00 0xf4000 0x00 0x2ac>;
223 pinctrl-single,function-mask = <0xffffffff>;
228 reg = <0x00 0x420000 0x00 0x1000>;
234 reg = <0x00 0x2400000 0x00 0x400>;
246 reg = <0x00 0x2410000 0x00 0x400>;
258 reg = <0x00 0x2420000 0x00 0x400>;
270 reg = <0x00 0x2430000 0x00 0x400>;
282 reg = <0x00 0x2440000 0x00 0x400>;
294 reg = <0x00 0x2450000 0x00 0x400>;
306 reg = <0x00 0x2460000 0x00 0x400>;
318 reg = <0x00 0x2470000 0x00 0x400>;
330 reg = <0x00 0x02800000 0x00 0x100>;
333 clocks = <&k3_clks 146 0>;
340 reg = <0x00 0x02810000 0x00 0x100>;
343 clocks = <&k3_clks 152 0>;
350 reg = <0x00 0x02820000 0x00 0x100>;
353 clocks = <&k3_clks 153 0>;
360 reg = <0x00 0x02830000 0x00 0x100>;
363 clocks = <&k3_clks 154 0>;
370 reg = <0x00 0x02840000 0x00 0x100>;
373 clocks = <&k3_clks 155 0>;
380 reg = <0x00 0x02850000 0x00 0x100>;
383 clocks = <&k3_clks 156 0>;
390 reg = <0x00 0x02860000 0x00 0x100>;
393 clocks = <&k3_clks 158 0>;
400 reg = <0x00 0x20000000 0x00 0x100>;
403 #size-cells = <0>;
412 reg = <0x00 0x20010000 0x00 0x100>;
415 #size-cells = <0>;
424 reg = <0x00 0x20020000 0x00 0x100>;
427 #size-cells = <0>;
436 reg = <0x00 0x20030000 0x00 0x100>;
439 #size-cells = <0>;
448 reg = <0x00 0x20100000 0x00 0x400>;
451 #size-cells = <0>;
453 clocks = <&k3_clks 141 0>;
459 reg = <0x00 0x20110000 0x00 0x400>;
462 #size-cells = <0>;
464 clocks = <&k3_clks 142 0>;
470 reg = <0x00 0x20120000 0x00 0x400>;
473 #size-cells = <0>;
475 clocks = <&k3_clks 143 0>;
481 reg = <0x00 0x00a00000 0x00 0x800>;
488 ti,interrupt-ranges = <0 32 16>;
493 reg = <0x0 0x00600000 0x0 0x100>;
502 ti,davinci-gpio-unbanked = <0>;
504 clocks = <&k3_clks 77 0>;
510 reg = <0x0 0x00601000 0x0 0x100>;
519 ti,davinci-gpio-unbanked = <0>;
521 clocks = <&k3_clks 78 0>;
527 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
536 ti,trm-icp = <0x2>;
538 ti,clkbuf-sel = <0x7>;
539 ti,otap-del-sel-legacy = <0x0>;
540 ti,otap-del-sel-mmc-hs = <0x0>;
541 ti,otap-del-sel-ddr52 = <0x5>;
542 ti,otap-del-sel-hs200 = <0x5>;
543 ti,itap-del-sel-legacy = <0xa>;
544 ti,itap-del-sel-mmc-hs = <0x1>;
550 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
555 ti,trm-icp = <0x2>;
556 ti,otap-del-sel-legacy = <0x8>;
557 ti,otap-del-sel-sd-hs = <0x0>;
558 ti,otap-del-sel-sdr12 = <0x0>;
559 ti,otap-del-sel-sdr25 = <0x0>;
560 ti,otap-del-sel-sdr50 = <0x8>;
561 ti,otap-del-sel-sdr104 = <0x7>;
562 ti,otap-del-sel-ddr50 = <0x4>;
563 ti,itap-del-sel-legacy = <0xa>;
564 ti,itap-del-sel-sd-hs = <0x1>;
565 ti,itap-del-sel-sdr12 = <0xa>;
566 ti,itap-del-sel-sdr25 = <0x1>;
567 ti,clkbuf-sel = <0x7>;
574 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
579 ti,trm-icp = <0x2>;
580 ti,otap-del-sel-legacy = <0x8>;
581 ti,otap-del-sel-sd-hs = <0x0>;
582 ti,otap-del-sel-sdr12 = <0x0>;
583 ti,otap-del-sel-sdr25 = <0x0>;
584 ti,otap-del-sel-sdr50 = <0x8>;
585 ti,otap-del-sel-sdr104 = <0x7>;
586 ti,otap-del-sel-ddr50 = <0x8>;
587 ti,itap-del-sel-legacy = <0xa>;
588 ti,itap-del-sel-sd-hs = <0xa>;
589 ti,itap-del-sel-sdr12 = <0xa>;
590 ti,itap-del-sel-sdr25 = <0x1>;
591 ti,clkbuf-sel = <0x7>;
597 reg = <0x00 0x0f900000 0x00 0x800>;
600 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
609 reg = <0x00 0x31000000 0x00 0x50000>;
610 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
611 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
622 reg = <0x00 0x0f910000 0x00 0x800>;
625 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
634 reg = <0x00 0x31100000 0x00 0x50000>;
635 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
636 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
647 reg = <0x00 0x0fc00000 0x00 0x70000>;
654 reg = <0x00 0x0fc40000 0x00 0x100>,
655 <0x05 0x00000000 0x01 0x00000000>;
659 cdns,trigger-address = <0x0>;
666 #size-cells = <0>;
675 reg = <0x00 0x08000000 0x00 0x200000>;
677 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
678 clocks = <&k3_clks 13 0>;
684 dmas = <&main_pktdma 0xc600 15>,
685 <&main_pktdma 0xc601 15>,
686 <&main_pktdma 0xc602 15>,
687 <&main_pktdma 0xc603 15>,
688 <&main_pktdma 0xc604 15>,
689 <&main_pktdma 0xc605 15>,
690 <&main_pktdma 0xc606 15>,
691 <&main_pktdma 0xc607 15>,
692 <&main_pktdma 0x4600 15>;
698 #size-cells = <0>;
706 ti,syscon-efuse = <&wkup_conf 0x200>;
720 reg = <0x00 0xf00 0x00 0x100>;
722 #size-cells = <0>;
723 clocks = <&k3_clks 13 0>;
731 reg = <0x00 0x3d000 0x00 0x400>;
743 reg = <0x00 0x30200000 0x00 0x1000>, /* common */
744 <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
745 <0x00 0x30206000 0x00 0x1000>, /* vid */
746 <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
747 <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
748 <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */
749 <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */
750 <0x00 0x30201000 0x00 0x1000>; /* common1 */
763 #size-cells = <0>;
769 reg = <0x00 0x2a000000 0x00 0x1000>;
775 reg = <0x00 0x29000000 0x00 0x200>;
786 reg = <0x00 0x23100000 0x00 0x100>;
788 clocks = <&k3_clks 51 0>;
796 reg = <0x00 0x23110000 0x00 0x100>;
798 clocks = <&k3_clks 52 0>;
806 reg = <0x00 0x23120000 0x00 0x100>;
808 clocks = <&k3_clks 53 0>;
815 reg = <0x00 0x20701000 0x00 0x200>,
816 <0x00 0x20708000 0x00 0x8000>;
824 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
830 reg = <0x00 0x0e000000 0x00 0x100>;
831 clocks = <&k3_clks 125 0>;
833 assigned-clocks = <&k3_clks 125 0>;
839 reg = <0x00 0x0e010000 0x00 0x100>;
840 clocks = <&k3_clks 126 0>;
842 assigned-clocks = <&k3_clks 126 0>;
848 reg = <0x00 0x0e020000 0x00 0x100>;
849 clocks = <&k3_clks 127 0>;
851 assigned-clocks = <&k3_clks 127 0>;
857 reg = <0x00 0x0e030000 0x00 0x100>;
858 clocks = <&k3_clks 128 0>;
860 assigned-clocks = <&k3_clks 128 0>;
866 reg = <0x00 0x0e0f0000 0x00 0x100>;
867 clocks = <&k3_clks 130 0>;
869 assigned-clocks = <&k3_clks 130 0>;
876 reg = <0x00 0x23000000 0x00 0x100>;
878 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
886 reg = <0x00 0x23010000 0x00 0x100>;
888 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
896 reg = <0x00 0x23020000 0x00 0x100>;
898 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
905 reg = <0x00 0x02b00000 0x00 0x2000>,
906 <0x00 0x02b08000 0x00 0x400>;
912 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
915 clocks = <&k3_clks 190 0>;
917 assigned-clocks = <&k3_clks 190 0>;
925 reg = <0x00 0x02b10000 0x00 0x2000>,
926 <0x00 0x02b18000 0x00 0x400>;
932 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
935 clocks = <&k3_clks 191 0>;
937 assigned-clocks = <&k3_clks 191 0>;
945 reg = <0x00 0x02b20000 0x00 0x2000>,
946 <0x00 0x02b28000 0x00 0x400>;
952 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
955 clocks = <&k3_clks 192 0>;
957 assigned-clocks = <&k3_clks 192 0>;