Lines Matching +full:i2c +full:- +full:gpio
1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "aspeed-g6.dtsi"
5 #include <dt-bindings/i2c/i2c.h>
6 #include <dt-bindings/gpio/aspeed-gpio.h>
7 #include <dt-bindings/leds/common.h>
11 compatible = "nvidia,gb200nvl-bmc", "aspeed,ast2600";
63 stdout-path = &uart5;
71 reserved-memory {
72 #address-cells = <1>;
73 #size-cells = <1>;
77 no-map;
84 record-size = <0x10000>; /* 64KB */
85 max-reason = <2>; /* KMSG_DUMP_OOPS */
91 compatible = "shared-dma-pool";
98 compatible = "shared-dma-pool";
104 compatible = "gpio-leds";
105 led-0 {
109 led-1 {
113 led-2 {
120 button-power {
121 label = "power-btn";
122 gpio = <&sgpiom0 156 GPIO_ACTIVE_LOW>;
124 button-uid {
125 label = "uid-btn";
126 gpio = <&sgpiom0 154 GPIO_ACTIVE_LOW>;
136 compatible = "jedec,spi-nor";
138 spi-max-frequency = <50000000>;
140 compatible = "fixed-partitions";
141 #address-cells = <1>;
142 #size-cells = <1>;
144 u-boot@0 {
147 label = "u-boot";
157 // 55292KB (extends to end of 64MB SPI - 4KB)
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_spi2_default>;
174 spi-max-frequency = <50000000>;
176 compatible = "fixed-partitions";
177 #address-cells = <1>;
178 #size-cells = <1>;
180 u-boot-env@0 {
183 label = "u-boot-env";
221 phy-mode = "rmii";
222 use-ncsi;
223 pinctrl-names = "default";
224 pinctrl-0 = <&pinctrl_rmii3_default>;
236 memory-region = <&video_engine_memory>;
252 gpio-line-names =
261 "RUN_POWER_FAULT_L-I","SYS_RST_IN_L-O",
262 "RUN_POWER_PG-I","PWR_BRAKE_L-O",
263 "SYS_RST_OUT_L-I","RUN_POWER_EN-O",
264 "L0L1_RST_REQ_OUT_L-I","SHDN_FORCE_L-O",
265 "L2_RST_REQ_OUT_L-I","SHDN_REQ_L-O",
266 "SHDN_OK_L-I","UID_LED_N-O",
267 "BMC_I2C1_FPGA_ALERT_L-I","SYS_FAULT_LED_N-O",
268 "BMC_I2C0_FPGA_ALERT_L-I","PWR_LED_N-O",
269 "FPGA_RSVD_FFU3-I","",
270 "FPGA_RSVD_FFU2-I","",
271 "FPGA_RSVD_FFU1-I","",
272 "FPGA_RSVD_FFU0-I","BMC_I2C_SSIF_ALERT_L-O",
273 "CPU_BOOT_DONE-I","JTAG_MUX_SELECT-O",
274 "SPI_BMC_FPGA_INT_L-I","RTC_CLR_L-O",
275 "THERM_BB_WARN_L-I","UART_MUX_SEL-O",
276 "THERM_BB_OVERT_L-I","",
277 "CPU0_UPHY3_PRSNT1_L-I","IOBRD0_RUN_POWER_EN-O",
278 "CPU0_UPHY3_PRSNT0_L-I","IOBRD1_RUN_POWER_EN-O",
279 "CPU0_UPHY2_PRSNT1_L-I","FPGA_RSVD_FFU4-O",
280 "CPU0_UPHY2_PRSNT0_L-I","FPGA_RSVD_FFU5-O",
281 "CPU0_UPHY1_PRSNT1_L-I","FPGA_RSVD_FFU6-O",
282 "CPU0_UPHY1_PRSNT0_L-I","FPGA_RSVD_FFU7-O",
283 "CPU0_UPHY0_PRSNT1_L-I","RSVD_NV_PLT_DETECT-O",
284 "CPU0_UPHY0_PRSNT0_L-I","SPI1_INT_L-O",
285 "CPU1_UPHY3_PRSNT1_L-I","",
286 "CPU1_UPHY3_PRSNT0_L-I","HMC_EROT_MUX_STATUS",
287 "CPU1_UPHY2_PRSNT1_L-I","",
288 "CPU1_UPHY2_PRSNT0_L-I","",
289 "CPU1_UPHY1_PRSNT1_L-I","",
290 "CPU1_UPHY1_PRSNT0_L-I","",
291 "CPU1_UPHY0_PRSNT1_L-I","",
292 "CPU1_UPHY0_PRSNT0_L-I","",
293 "FAN1_PRESENT_L-I","",
294 "FAN0_PRESENT_L-I","",
296 "IPEX_CABLE_PRSNT_L-I","",
297 "M2_1_PRSNT_L-I","",
298 "M2_0_PRSNT_L-I","",
299 "CPU1_UPHY4_PRSNT1_L-I","",
300 "CPU0_UPHY4_PRSNT0_L-I","",
302 "I2C_RTC_ALERT_L-I","",
303 "FAN7_PRESENT_L-I","",
304 "FAN6_PRESENT_L-I","",
305 "FAN5_PRESENT_L-I","",
306 "FAN4_PRESENT_L-I","",
307 "FAN3_PRESENT_L-I","",
308 "FAN2_PRESENT_L-I","",
309 "IOBRD0_IOX_INT_L-I","",
310 "IOBRD1_PRSNT_L-I","",
311 "IOBRD0_PRSNT_L-I","",
312 "IOBRD1_PWR_GOOD-I","",
313 "IOBRD0_PWR_GOOD-I","",
316 "FAN_FAIL_IN_L-I","",
320 "PDB_CABLE_PRESENT_L-I","",
322 "CHASSIS_PWR_BRK_L-I","",
324 "IOBRD1_IOX_INT_L-I","",
325 "10GBE_SMBALRT_L-I","",
326 "PCIE_WAKE_L-I","",
327 "I2C_M21_ALERT_L-I","",
328 "I2C_M20_ALERT_L-I","",
329 "TRAY_FAST_SHDN_L-I","",
330 "UID_BTN_N-I","",
331 "PWR_BTN_L-I","",
332 "PSU_SMB_ALERT_L-I","",
335 "NODE_LOC_ID[0]-I","",
336 "NODE_LOC_ID[1]-I","",
337 "NODE_LOC_ID[2]-I","",
338 "NODE_LOC_ID[3]-I","",
339 "NODE_LOC_ID[4]-I","",
340 "NODE_LOC_ID[5]-I","",
341 "FAN10_PRESENT_L-I","",
342 "FAN9_PRESENT_L-I","",
343 "FAN8_PRESENT_L-I","",
344 "FPGA1_READY_HMC-I","",
345 "DP_HPD-I","",
346 "HMC_I2C3_FPGA_ALERT_L-I","",
347 "HMC_I2C2_FPGA_ALERT_L-I","",
348 "FPGA0_READY_HMC-I","",
353 "LEAK_DETECT_ALERT_L-I","",
354 "MOD1_B2B_CABLE_PRESENT_L-I","",
355 "MOD1_CLINK_CABLE_PRESENT_L-I","",
356 "FAN11_PRESENT_L-I","",
386 clock-frequency = <400000>;
388 ssif-bmc@10 {
389 compatible = "ssif-bmc";
395 // BMC_I2C1_FPGA - Secondary FPGA
399 clock-frequency = <400000>;
400 multi-master;
404 // BMC_I2C0_FPGA - Primary FPGA
408 clock-frequency = <400000>;
409 multi-master;
422 clock-frequency = <400000>;
425 exp4: gpio@21 {
428 gpio-controller;
429 #gpio-cells = <2>;
430 interrupt-controller;
431 #interrupt-cells = <2>;
432 interrupt-parent = <&gpio1>;
434 gpio-line-names =
435 "RTC_MUX_SEL-O",
436 "PCI_MUX_SEL-O",
437 "TPM_MUX_SEL-O",
438 "FAN_MUX-SEL-O",
439 "SGMII_MUX_SEL-O",
440 "DP_MUX_SEL-O",
441 "UPHY3_USB_SEL-O",
442 "NCSI_MUX_SEL-O",
443 "BMC_PHY_RST-O",
444 "RTC_CLR_L-O",
445 "BMC_12V_CTRL-O",
446 "PS_RUN_IO0_PG-I",
455 // Module 0/1 I2C MUX x3
458 clock-frequency = <400000>;
459 multi-master;
461 i2c-mux@71 {
463 #address-cells = <1>;
464 #size-cells = <0>;
466 i2c-mux-idle-disconnect;
468 imux16: i2c@0 {
469 #address-cells = <1>;
470 #size-cells = <0>;
474 imux17: i2c@1 {
475 #address-cells = <1>;
476 #size-cells = <0>;
479 i2c-mux@74 {
481 #address-cells = <1>;
482 #size-cells = <0>;
484 i2c-mux-idle-disconnect;
486 i2c17mux0: i2c@0 {
487 #address-cells = <1>;
488 #size-cells = <0>;
492 i2c17mux1: i2c@1 {
493 #address-cells = <1>;
494 #size-cells = <0>;
498 i2c17mux2: i2c@2 {
499 #address-cells = <1>;
500 #size-cells = <0>;
504 i2c17mux3: i2c@3 {
505 #address-cells = <1>;
506 #size-cells = <0>;
512 imux18: i2c@2 {
513 #address-cells = <1>;
514 #size-cells = <0>;
518 imux19: i2c@3 {
519 #address-cells = <1>;
520 #size-cells = <0>;
525 i2c-mux@72 {
527 #address-cells = <1>;
528 #size-cells = <0>;
530 i2c-mux-idle-disconnect;
532 imux20: i2c@0 {
533 #address-cells = <1>;
534 #size-cells = <0>;
538 imux21: i2c@1 {
539 #address-cells = <1>;
540 #size-cells = <0>;
543 gpio@21 {
546 gpio-controller;
547 #gpio-cells = <2>;
548 gpio-line-names =
549 "RST_CX_0_L-O",
550 "RST_CX_1_L-O",
551 "CX0_SSD0_PRSNT_L-I",
552 "CX1_SSD1_PRSNT_L-I",
553 "CX_BOOT_CMPLT_CX0-I",
554 "CX_BOOT_CMPLT_CX1-I",
555 "CX_TWARN_CX0_L-I",
556 "CX_TWARN_CX1_L-I",
557 "CX_OVT_SHDN_CX0-I",
558 "CX_OVT_SHDN_CX1-I",
559 "FNP_L_CX0-O",
560 "FNP_L_CX1-O",
562 "MCU_GPIO-I",
563 "MCU_RST_N-O",
564 "MCU_RECOVERY_N-O";
568 imux22: i2c@2 {
569 #address-cells = <1>;
570 #size-cells = <0>;
574 imux23: i2c@3 {
575 #address-cells = <1>;
576 #size-cells = <0>;
581 i2c-mux@73 {
583 #address-cells = <1>;
584 #size-cells = <0>;
586 i2c-mux-idle-disconnect;
588 imux24: i2c@0 {
589 #address-cells = <1>;
590 #size-cells = <0>;
594 imux25: i2c@1 {
595 #address-cells = <1>;
596 #size-cells = <0>;
599 i2c-mux@70 {
601 #address-cells = <1>;
602 #size-cells = <0>;
604 i2c-mux-idle-disconnect;
606 i2c25mux0: i2c@0 {
607 #address-cells = <1>;
608 #size-cells = <0>;
612 i2c25mux1: i2c@1 {
613 #address-cells = <1>;
614 #size-cells = <0>;
618 i2c25mux2: i2c@2 {
619 #address-cells = <1>;
620 #size-cells = <0>;
624 i2c25mux3: i2c@3 {
625 #address-cells = <1>;
626 #size-cells = <0>;
632 imux26: i2c@2 {
633 #address-cells = <1>;
634 #size-cells = <0>;
638 imux27: i2c@3 {
639 #address-cells = <1>;
640 #size-cells = <0>;
645 i2c-mux@75 {
647 #address-cells = <1>;
648 #size-cells = <0>;
650 i2c-mux-idle-disconnect;
652 imux28: i2c@0 {
653 #address-cells = <1>;
654 #size-cells = <0>;
658 imux29: i2c@1 {
659 #address-cells = <1>;
660 #size-cells = <0>;
663 i2c-mux@74 {
665 #address-cells = <1>;
666 #size-cells = <0>;
668 i2c-mux-idle-disconnect;
670 i2c29mux0: i2c@0 {
671 #address-cells = <1>;
672 #size-cells = <0>;
676 i2c29mux1: i2c@1 {
677 #address-cells = <1>;
678 #size-cells = <0>;
682 i2c29mux2: i2c@2 {
683 #address-cells = <1>;
684 #size-cells = <0>;
688 i2c29mux3: i2c@3 {
689 #address-cells = <1>;
690 #size-cells = <0>;
696 imux30: i2c@2 {
697 #address-cells = <1>;
698 #size-cells = <0>;
702 imux31: i2c@3 {
703 #address-cells = <1>;
704 #size-cells = <0>;
709 i2c-mux@76 {
711 #address-cells = <1>;
712 #size-cells = <0>;
714 i2c-mux-idle-disconnect;
716 imux32: i2c@0 {
717 #address-cells = <1>;
718 #size-cells = <0>;
722 imux33: i2c@1 {
723 #address-cells = <1>;
724 #size-cells = <0>;
727 gpio@21 {
730 gpio-controller;
731 #gpio-cells = <2>;
732 gpio-line-names =
733 "SEC_RST_CX_0_L-O",
734 "SEC_RST_CX_1_L-O",
735 "SEC_CX0_SSD0_PRSNT_L-I",
736 "SEC_CX1_SSD1_PRSNT_L-I",
737 "SEC_CX_BOOT_CMPLT_CX0-I",
738 "SEC_CX_BOOT_CMPLT_CX1-I",
739 "SEC_CX_TWARN_CX0_L-I",
740 "SEC_CX_TWARN_CX1_L-I",
741 "SEC_CX_OVT_SHDN_CX0-I",
742 "SEC_CX_OVT_SHDN_CX1-I",
743 "SEC_FNP_L_CX0-O",
744 "SEC_FNP_L_CX1-O",
746 "SEC_MCU_GPIO-I",
747 "SEC_MCU_RST_N-O",
748 "SEC_MCU_RECOVERY_N-O";
752 imux34: i2c@2 {
753 #address-cells = <1>;
754 #size-cells = <0>;
758 imux35: i2c@3 {
759 #address-cells = <1>;
760 #size-cells = <0>;
765 i2c-mux@77 {
767 #address-cells = <1>;
768 #size-cells = <0>;
770 i2c-mux-idle-disconnect;
772 imux36: i2c@0 {
773 #address-cells = <1>;
774 #size-cells = <0>;
778 imux37: i2c@1 {
779 #address-cells = <1>;
780 #size-cells = <0>;
784 imux38: i2c@2 {
785 #address-cells = <1>;
786 #size-cells = <0>;
790 imux39: i2c@3 {
791 #address-cells = <1>;
792 #size-cells = <0>;
803 clock-frequency = <400000>;
808 shunt-resistor-micro-ohms = <190>;
815 shunt-resistor-micro-ohms = <190>;
844 clock-frequency = <400000>;
845 multi-master;
853 clock-frequency = <400000>;
856 exp0: gpio@20 {
859 gpio-controller;
860 #gpio-cells = <2>;
861 interrupt-controller;
862 #interrupt-cells = <2>;
863 interrupt-parent = <&gpio1>;
865 gpio-line-names =
866 "FPGA_THERM_OVERT_L-I",
867 "FPGA_READY_BMC-I",
868 "HMC_BMC_DETECT-O",
869 "HMC_PGOOD-O",
871 "BMC_STBY_CYCLE-O",
872 "FPGA_EROT_FATAL_ERROR_L-I",
873 "WP_HW_EXT_CTRL_L-O",
874 "EROT_FPGA_RST_L-O",
875 "FPGA_EROT_RECOVERY_L-O",
876 "BMC_EROT_FPGA_SPI_MUX_SEL-O",
877 "USB_HUB_RESET_L-O",
878 "NCSI_CS1_SEL-O",
879 "SGPIO_EN_L-O",
880 "B2B_IOEXP_INT_L-I",
881 "I2C_BUS_MUX_RESET_L-O";
885 exp1: gpio@21 {
888 gpio-controller;
889 #gpio-cells = <2>;
890 interrupt-controller;
891 #interrupt-cells = <2>;
892 interrupt-parent = <&gpio1>;
894 gpio-line-names =
895 "SEC_FPGA_THERM_OVERT_L-I",
896 "SEC_FPGA_READY_BMC-I",
901 "SEC_FPGA_EROT_FATAL_ERROR_L-I",
902 "SEC_WP_HW_EXT_CTRL_L-O",
903 "SEC_EROT_FPGA_RST_L-O",
904 "SEC_FPGA_EROT_RECOVERY_L-O",
905 "SEC_BMC_EROT_FPGA_SPI_MUX_SEL-O",
906 "SEC_USB2_HUB_RST_L-O",
910 "SEC_I2C_BUS_MUX_RESET_L-O";
914 exp2: gpio@27 {
917 gpio-controller;
918 #gpio-cells = <2>;
919 interrupt-controller;
920 #interrupt-cells = <2>;
921 interrupt-parent = <&gpio1>;
923 gpio-line-names =
924 "HMC_PRSNT_L-I",
925 "HMC_READY-I",
926 "HMC_EROT_FATAL_ERROR_L-I",
927 "I2C_MUX_SEL-O",
928 "HMC_EROT_SPI_MUX_SEL-O",
929 "HMC_EROT_RECOVERY_L-O",
930 "HMC_EROT_RST_L-O",
931 "GLOBAL_WP_HMC-O",
932 "FPGA_RST_L-O",
933 "USB2_HUB_RST-O",
934 "CPU_UART_MUX_SEL-O",
943 exp3: gpio@74 {
946 gpio-controller;
947 #gpio-cells = <2>;
948 interrupt-controller;
949 #interrupt-cells = <2>;
950 interrupt-parent = <&gpio1>;
952 gpio-line-names =
977 clock-frequency = <400000>;
979 // BMC FRU EEPROM - 256 bytes
1007 clock-frequency = <100000>;
1008 multi-master;
1010 //E1.S drive slot 0-3
1011 i2c-mux@77 {
1013 #address-cells = <1>;
1014 #size-cells = <0>;
1016 i2c-mux-idle-disconnect;
1018 e1si2c0: i2c@0 {
1019 #address-cells = <1>;
1020 #size-cells = <0>;
1024 e1si2c1: i2c@1 {
1025 #address-cells = <1>;
1026 #size-cells = <0>;
1030 e1si2c2: i2c@2 {
1031 #address-cells = <1>;
1032 #size-cells = <0>;
1036 e1si2c3: i2c@3 {
1037 #address-cells = <1>;
1038 #size-cells = <0>;
1047 clock-frequency = <100000>;
1048 multi-master;
1050 //E1.S drive slot 4-7
1051 i2c-mux@77 {
1053 #address-cells = <1>;
1054 #size-cells = <0>;
1056 i2c-mux-idle-disconnect;
1058 e1si2c4: i2c@0 {
1059 #address-cells = <1>;
1060 #size-cells = <0>;
1064 e1si2c5: i2c@1 {
1065 #address-cells = <1>;
1066 #size-cells = <0>;
1070 e1si2c6: i2c@2 {
1071 #address-cells = <1>;
1072 #size-cells = <0>;
1076 e1si2c7: i2c@3 {
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1089 gpio-line-names =
1090 /*A0-A7*/ "", "", "", "", "", "", "", "",
1091 /*B0-B7*/ "", "", "", "", "", "", "", "",
1092 /*C0-C7*/ "SGPIO_I2C_MUX_SEL-O", "", "", "", "", "", "", "",
1093 /*D0-D7*/ "", "", "", "UART1_MUX_SEL-O", "", "FPGA_PEX_RST_L-O", "", "",
1094 /*E0-E7*/ "RTL8221_PHY_RST_L-O", "RTL8211_PHY_INT_L-I", "", "UART3_MUX_SEL-O",
1095 "", "", "", "SGPIO_BMC_EN-O",
1096 /*F0-F7*/ "", "", "", "", "", "", "", "",
1097 /*G0-G7*/ "", "", "", "", "", "", "", "",
1098 /*H0-H7*/ "", "", "", "", "", "", "", "",
1099 /*I0-I7*/ "", "", "", "", "", "QSPI2_RST_L-O", "GLOBAL_WP_BMC-O", "BMC_DDR4_TEN-O",
1100 /*J0-J7*/ "", "", "", "", "", "", "", "",
1101 /*K0-K7*/ "", "", "", "", "", "", "", "",
1102 /*L0-L7*/ "", "", "", "", "", "", "", "",
1103 /*M0-M7*/ "PCIE_EP_RST_EN-O", "BMC_FRU_WP-O", "HMC_RESET_L-O", "STBY_POWER_EN-O",
1104 "STBY_POWER_PG-I", "PCIE_EP_RST_L-O", "", "",
1105 /*N0-N7*/ "", "", "", "", "", "", "", "",
1106 /*O0-O7*/ "", "", "", "", "", "", "", "",
1107 /*P0-P7*/ "", "", "", "", "", "", "", "",
1108 /*Q0-Q7*/ "", "", "", "", "", "", "", "",
1109 /*R0-R7*/ "", "", "", "", "", "", "", "",
1110 /*S0-S7*/ "", "", "", "", "", "", "", "",
1111 /*T0-T7*/ "", "", "", "", "", "", "", "",
1112 /*U0-U7*/ "", "", "", "", "", "", "", "",
1113 /*V0-V7*/ "AP_EROT_REQ-O", "EROT_AP_GNT-I", "", "","PCB_TEMP_ALERT-I", "","", "",
1114 /*W0-W7*/ "", "", "", "", "", "", "", "",
1115 /*X0-X7*/ "", "", "TPM_MUX_SEL-O", "", "", "", "", "",
1116 /*Y0-Y7*/ "", "", "", "EMMC_RST-O", "","", "", "",
1117 /*Z0-Z7*/ "BMC_READY-O","", "", "", "", "", "", "";
1122 gpio-line-names =
1123 /*A0-A7*/ "", "", "", "", "", "", "", "",
1124 /*B0-B7*/ "", "", "", "", "", "", "IO_EXPANDER_INT_L-I","",
1125 /*C0-C7*/ "", "", "", "", "", "", "", "",
1126 /*D0-D7*/ "", "", "", "", "", "", "SPI_HOST_TPM_RST_L-O", "SPI_BMC_FPGA_INT_L-I",
1127 /*E0-E7*/ "", "", "", "", "", "", "", "";