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Revision tags: v00.04.15 |
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591e1cf0 |
| 02-May-2023 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi: Add usage example for write protect APIs
Implement the demostration scenario for command filter
and write address filter APIs.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Chang
spi: Add usage example for write protect APIs
Implement the demostration scenario for command filter
and write address filter APIs.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: Ia1e67aa222925a711e98148ccbf37741d7ae7812
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Revision tags: v00.04.14 |
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| #
838fb1e6 |
| 18-Feb-2023 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi-nor: Disable hold/reset pin on MT25QL02G
Disable hold/reset pin function on MT25QL02G flash part.
If QSPI mode is used and the IO rising time is not good,
the flash will be in hold/reset status
spi-nor: Disable hold/reset pin on MT25QL02G
Disable hold/reset pin function on MT25QL02G flash part.
If QSPI mode is used and the IO rising time is not good,
the flash will be in hold/reset status when the next QSPI
command is sent.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I39a7b043b6c122b1bf40ce9a29e3202f3ce536ef
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Revision tags: v00.04.13, v00.04.12, v00.04.11 |
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| #
eaad4c09 |
| 24-Apr-2022 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi-nor: Porting for S25HL series
Add Cypress S25HL series flash.
Sync code base from u-boot mainline.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I10a0d6d51f2500696b7c0a
spi-nor: Porting for S25HL series
Add Cypress S25HL series flash.
Sync code base from u-boot mainline.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I10a0d6d51f2500696b7c0abc41e935fda90321f0
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Revision tags: v00.04.10, v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01 |
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| #
878b2ba4 |
| 14-May-2021 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi-nor: Add QE bit setting function for GD25Q256E
QE bit is located in status register 2 of GD25Q256E,
The setting method of status register 2 is different
from Winbond (using 01h command). Thus, a
spi-nor: Add QE bit setting function for GD25Q256E
QE bit is located in status register 2 of GD25Q256E,
The setting method of status register 2 is different
from Winbond (using 01h command). Thus, a new setting
function is needed.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I9a48a2be5eed505502296cbdc7bf0b5e56291614
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Revision tags: v00.04.00 |
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| #
a25e89c3 |
| 28-Apr-2021 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi-nor: Porting MT25Q02G flash part
Due to bad raising timing, hold/reset pin feature should
be disabled if quad mode is enabled. Otherwise, flash will
be hold when command is send to flash.
Signe
spi-nor: Porting MT25Q02G flash part
Due to bad raising timing, hold/reset pin feature should
be disabled if quad mode is enabled. Otherwise, flash will
be hold when command is send to flash.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I82e91646097822793c53dcf896c43ce26756acbb
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Revision tags: v2021.04, v00.03.03 |
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| #
cd800046 |
| 17-Jan-2021 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi-nor: Add support for Cypress s25hl-t/s25hs-t
Only support 1-1-1 SPI write format.
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Revision tags: v2021.01 |
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| #
3d9814f8 |
| 16-Oct-2020 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
Merge branch 'spi' into aspeed-dev-v2019.04
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| #
00554b9b |
| 16-Oct-2020 |
Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> |
spi-nor: ISSI flash model support
Support ISSI flash models, is25lp256 and is25lp512m.
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Revision tags: v2020.10, v2020.07, v00.02.13, v2020.04, v2020.01, v2019.10, v00.02.05, v00.02.04, v00.02.03, v00.02.02, v00.02.01, v2019.07, v00.02.00, v2019.04 |
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| #
50e24381 |
| 07-Feb-2019 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-spi
- SPI-NOR support
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| #
8c927809 |
| 04-Feb-2019 |
Vignesh R <vigneshr@ti.com> |
mtd: spi: spi-nor-core: Add back U-Boot specific features
For legacy reasons, we will have to keep around U-Boot specific
SPI_FLASH_BAR and SPI_TX_BYTE. Add them back to the new framework
Signed-of
mtd: spi: spi-nor-core: Add back U-Boot specific features
For legacy reasons, we will have to keep around U-Boot specific
SPI_FLASH_BAR and SPI_TX_BYTE. Add them back to the new framework
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
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| #
7aeedac0 |
| 04-Feb-2019 |
Vignesh R <vigneshr@ti.com> |
mtd: spi: Port SPI NOR framework from Linux
Current U-Boot SPI NOR support (sf layer) is quite outdated as it does not
support 4 byte addressing opcodes, SFDP table parsing and different types of
qu
mtd: spi: Port SPI NOR framework from Linux
Current U-Boot SPI NOR support (sf layer) is quite outdated as it does not
support 4 byte addressing opcodes, SFDP table parsing and different types of
quad mode enable sequences. Many newer flashes no longer support BANK
registers used by sf layer to a access >16MB of flash address space.
So, sync SPI NOR framework from Linux v4.19 that supports all the
above features. Start with basic sync up that brings in basic framework
subsequent commits will bring in more features.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
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