Revision tags: v00.04.15, v00.04.14, v00.04.13, v00.04.12, v00.04.11, v00.04.10, v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01, v00.04.00, v2021.04, v00.03.03, v2021.01, v2020.10, v2020.07, v00.02.13, v2020.04, v2020.01, v2019.10, v00.02.05, v00.02.04, v00.02.03, v00.02.02, v00.02.01, v2019.07, v00.02.00, v2019.04, v2018.07, v2018.03 |
|
#
c4cb6e64 |
| 19-Jan-2018 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-arc
|
#
075cbae1 |
| 16-Jan-2018 |
Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> |
ARC: HSDK: CGU: Update AXI, TUN, ARC clock options
Update default AXI, TUN, ARC clock set options: instead of changing only IDIV divider settings adjust also domain PLL settings.
Add support of TUN
ARC: HSDK: CGU: Update AXI, TUN, ARC clock options
Update default AXI, TUN, ARC clock set options: instead of changing only IDIV divider settings adjust also domain PLL settings.
Add support of TUN_ROM and TUN_PWM clocks (subclocks of TUNN_PLL)
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
show more ...
|
Revision tags: v2018.01 |
|
#
6f1ee8a4 |
| 11-Dec-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-arc
|
#
e80dac0a |
| 10-Dec-2017 |
Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> |
ARC: clk: introduce HSDK CGU clock driver
Synopsys HSDK clock controller generates and supplies clocks to various controllers and peripherals within the SoC.
Each clock has assigned identifier and
ARC: clk: introduce HSDK CGU clock driver
Synopsys HSDK clock controller generates and supplies clocks to various controllers and peripherals within the SoC.
Each clock has assigned identifier and client device tree nodes can use this identifier to specify the clock which they consume. All available clocks are defined as preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device tree sources.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
show more ...
|