| 543049ab | 10-Jul-2018 |
Jagan Teki <jagan@amarulasolutions.com> |
usb: host: Drop [e-o]hci-sunxi drivers
Now Allwinner platform is all set to use Generic USB
controller drivers, so remove the legacy sunxi drivers.
Signed-off-by: Jagan Teki <jagan@amarulasolutions
usb: host: Drop [e-o]hci-sunxi drivers
Now Allwinner platform is all set to use Generic USB
controller drivers, so remove the legacy sunxi drivers.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
show more ...
|
| 24667041 | 21-Sep-2018 |
Ramon Fried <ramon.fried@gmail.com> |
usb: ehci-msm: Add init_after_reset for CI_UDC
MSM uses the chipidea controller IP, however it requires
to reinit the phy after controller reset. in EHCI mode there's a
dedicated callback for it.
In
usb: ehci-msm: Add init_after_reset for CI_UDC
MSM uses the chipidea controller IP, however it requires
to reinit the phy after controller reset. in EHCI mode there's a
dedicated callback for it.
In device mode however there's no such callback.
Add implementaion of ci_init_after_reset() to implement the above
requirement in case CI_UDC driver is used.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
show more ...
|
| 2df49234 | 21-Sep-2018 |
Ramon Fried <ramon.fried@gmail.com> |
ehci: msm: Add missing platdata
platdata_auto_alloc_size was not initialized in structure.
Caused null pointer dereference when configuring device as
gadget.
Signed-off-by: Ramon Fried <ramon.fried
ehci: msm: Add missing platdata
platdata_auto_alloc_size was not initialized in structure.
Caused null pointer dereference when configuring device as
gadget.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
show more ...
|
| 88c34b8d | 28-Aug-2018 |
Ley Foon Tan <ley.foon.tan@intel.com> |
usb: dwc2: Add reset ctrl to driver
Add code to reset all reset signals as in usb DT node. A reset property
is an optional feature, so only print out a warning and do not fail if a
reset property is
usb: dwc2: Add reset ctrl to driver
Add code to reset all reset signals as in usb DT node. A reset property
is an optional feature, so only print out a warning and do not fail if a
reset property is not present.
If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
show more ...
|
| 1335e774 | 07-Aug-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
usb: ehci: Add PHY support to ehci-pci
Add support for operating a PHY attached to ehci-pci. There are
systems where the EHCI controller is internally wired to a PCI
bus and has a PHY connected to i
usb: ehci: Add PHY support to ehci-pci
Add support for operating a PHY attached to ehci-pci. There are
systems where the EHCI controller is internally wired to a PCI
bus and has a PHY connected to it as well, ie. the R-Car Gen2.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
show more ...
|
| 0bc846a7 | 04-Jul-2018 |
Andre Przywara <andre.przywara@arm.com> |
sunxi: A64: OHCI: prevent turning off shared USB clock
On the A64 the clock for the first USB controller is actually the parent
of the clock for the second controller, so turning them off in that or
sunxi: A64: OHCI: prevent turning off shared USB clock
On the A64 the clock for the first USB controller is actually the parent
of the clock for the second controller, so turning them off in that order
makes the system hang.
Fix this by only turning off *both* clocks when the *last* OHCI controller
is brought down. This covers the case when only one controller is used.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
show more ...
|
| 9c22aec4 | 28-Jun-2018 |
Jagan Teki <jagannadh.teki@gmail.com> |
usb: sunxi: Use proper reg_mask for clock gate, reset
Masking clock gate, reset register bits based on the
probed controller is proper only due to the assumption
that masking should start with 0 eve
usb: sunxi: Use proper reg_mask for clock gate, reset
Masking clock gate, reset register bits based on the
probed controller is proper only due to the assumption
that masking should start with 0 even thought the controller
has separate PHY or shared between OTG.
unfortunately these are fixed due to lack of separate
clock, reset drivers.
Say for example EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG)
so we need to start reg_mask 0 - 2.
This patch calculated the mask, based on the register base
so that we can get the proper bits to set with respect to
probed controller.
We even do this masking by using PHY index specifier from dt,
but dev_read_addr_size is failing for 64-bit boards.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
show more ...
|