Merge tag 'xilinx-for-v2019.04' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2019.04

tools:
- Fix zynqmpimage generation

zynq:
- Some configs/Kconfig/DT updates
- Enable REMAKE_ELF a

Merge tag 'xilinx-for-v2019.04' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2019.04

tools:
- Fix zynqmpimage generation

zynq:
- Some configs/Kconfig/DT updates
- Enable REMAKE_ELF and OF_SEPARATE
- Topic boards update
- i2c cleanups and conversion to DM_I2C

zynqmp:
- Some configs/Kconfig/DT updates
- Board config cleanup
- Move arch folder to mach-zynqmp

versal:
- Enable DM_I2C, CMD_DM

zynq-gem:
- Fix driver cache handling

i2c:
- Live tree simple update

phy:
- Fixed phy cleanup

travis:
- Wire Versal SoC

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zynq-gem: Use appropriate cache flush/invalidate for RX and TX

The cache was only flushed before *transmitting* packets, but not
when receiving them, leading to an issue where new packets were
hande

zynq-gem: Use appropriate cache flush/invalidate for RX and TX

The cache was only flushed before *transmitting* packets, but not
when receiving them, leading to an issue where new packets were
handed to the receive handler with old contents in cache. This
only happens when a lot of packets are received without sending
packages every now and then. Also flushing the receive buffers
in the transmit function makes no sense and can be removed.

Signed-off-by: Stefan Theil <stefan.theil@mixed-mode.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

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Merge tag 'xilinx-for-v2019.01' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2019.01

microblaze:
- Use default functions for memory decoding
- Showing model from DT

zynq:
- Fix spi f

Merge tag 'xilinx-for-v2019.01' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2019.01

microblaze:
- Use default functions for memory decoding
- Showing model from DT

zynq:
- Fix spi flash DTs
- Fix zynq_help_text with CONFIG_SYS_LONGHELP
- Tune cse/mini configurations
- Enabling cse/mini testing with current targets

zynqmp:
- Enable gzip SPL support
- Fix chip detection logic
- Tune mini configurations
- DT fixes(spi-flash, models, clocks, etc)
- Add support for OF_SEPARATE configurations
- Enabling mini testing with current targets
- Add mini mtest configuration
- Some minor config setting

nand:
- arasan: Add subpage configuration

net:
- gem: Add 64bit DMA support

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net: zynq_gem: Add check for 64-bit dma support by hardware

This patch throws an error if 64-bit support is expected
but DMA hardware is not capable of 64-bit support. It also
prints a debug message

net: zynq_gem: Add check for 64-bit dma support by hardware

This patch throws an error if 64-bit support is expected
but DMA hardware is not capable of 64-bit support. It also
prints a debug message if DMA is capable of 64-bit but not
using it.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>

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net: zynq_gem: Added 64-bit addressing support

This patch adds 64-bit addressing support for zynq gem.
This means it can perform send and receive operations on
64-bit address buffers.

Signed-off-by

net: zynq_gem: Added 64-bit addressing support

This patch adds 64-bit addressing support for zynq gem.
This means it can perform send and receive operations on
64-bit address buffers.

Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>

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Merge git://git.denx.de/u-boot-microblaze

Xilinx changes for v2018.11-rc2-v2

FPGA:
- Fix SPL fpga loading from FIT

ARM64:
- Fix gic accesses in EL2/EL1

Xilinx:
- Add dlc20 board support
- Add Ver

Merge git://git.denx.de/u-boot-microblaze

Xilinx changes for v2018.11-rc2-v2

FPGA:
- Fix SPL fpga loading from FIT

ARM64:
- Fix gic accesses in EL2/EL1

Xilinx:
- Add dlc20 board support
- Add Versal board support
- Sync defconfigs
- Enable MP via Kconfig
- Add missing efuse node
- Enable CDC for zcu100

cmd:
- Fix kgdb Kconfig dependency

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net: gem: Do not setup any clock for Xilinx SoC Versal

Xilinx SoC Versal is using fixed clock where setting rate is not supported.
That's why workaround the driver till real clock driver is supporte

net: gem: Do not setup any clock for Xilinx SoC Versal

Xilinx SoC Versal is using fixed clock where setting rate is not supported.
That's why workaround the driver till real clock driver is supported.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

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Merge tag 'xilinx-for-v2018.11' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2018.11

- Handle BOARD_LATE_INIT via Kconfig

SPL:
- Enable GZIP for all partitions types(not only for ker

Merge tag 'xilinx-for-v2018.11' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2018.11

- Handle BOARD_LATE_INIT via Kconfig

SPL:
- Enable GZIP for all partitions types(not only for kernel)

ZynqMP:
- Rearrange pmufw version handling
- Support newer PMUFW with improved fpga load sequence

Zynq:
- Cleanup config file
- Simplify zybo config by enabling option via Kconfig

net:
- Fix gems max-speed property reading
- Enable support for fixed-link phys

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net: zynq_gem: Add support for fixed-link phy

Based on dt-specs fixed-link doesn't require phy-handle to be used.
Fix driver to only read phy related setting when phy-handle is found.

Signed-off-by

net: zynq_gem: Add support for fixed-link phy

Based on dt-specs fixed-link doesn't require phy-handle to be used.
Fix driver to only read phy related setting when phy-handle is found.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

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net: zynq_gem: Fix reading of max-speed property

max-speed property is part of phynode and it has to be
read using ofnode_read_u32_default(). This fixes the issue
of incorrect max-speed read from DT

net: zynq_gem: Fix reading of max-speed property

max-speed property is part of phynode and it has to be
read using ofnode_read_u32_default(). This fixes the issue
of incorrect max-speed read from DT.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

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Merge branch 'master' of git://git.denx.de/u-boot-net

net: zynq_gem: convert to use livetree

This patch updates the zynq gem driver to support livetree.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Vipul Ku

net: zynq_gem: convert to use livetree

This patch updates the zynq gem driver to support livetree.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

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drivers: net: zynq_gem: fix phy dt node setting

Now zynq_gem driver will overwrite UCLASS_ETH node when PHY is
connected and configured which is not correct.
Use struct phydev->node instead.

Signed

drivers: net: zynq_gem: fix phy dt node setting

Now zynq_gem driver will overwrite UCLASS_ETH node when PHY is
connected and configured which is not correct.
Use struct phydev->node instead.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

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Merge branch 'master' of git://git.denx.de/u-boot-net

net: zynq_gem: Initialize val variable in zynq_gem_miiphy_read()

phyread can timeout and val will contain random value. Initialize it to
zero not to report random value in case of error.

Signed-off

net: zynq_gem: Initialize val variable in zynq_gem_miiphy_read()

phyread can timeout and val will contain random value. Initialize it to
zero not to report random value in case of error.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

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Merge branch 'master' of git://git.denx.de/u-boot-net

net: gem: Check return value from memalign/malloc

Functions can return NULL in case of error that's why checking return
value is needed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-

net: gem: Check return value from memalign/malloc

Functions can return NULL in case of error that's why checking return
value is needed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

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net: zynq_gem: Initialize phyreg variable

In case of phyread()/phy_setup_op() timeout code is working with
uninitialized phyreg variable. Initialize this variable to make sure
that code it not worki

net: zynq_gem: Initialize phyreg variable

In case of phyread()/phy_setup_op() timeout code is working with
uninitialized phyreg variable. Initialize this variable to make sure
that code it not working with random value.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

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net: zynq_gem: Fix return type for phy...()

wait_for_bit_le32 returns negative value on failure. Fix phy...() to
handle these failures properly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com

net: zynq_gem: Fix return type for phy...()

wait_for_bit_le32 returns negative value on failure. Fix phy...() to
handle these failures properly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

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SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So

SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>

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Merge git://git.denx.de/u-boot-net

net: zynq_gem: Use max-speed property from dt

Add support to use max-speed property from dt for
determining the supported speed. Use 1000Mbps as
default.

Signed-off-by: Siva Durga Prasad Paladugu <

net: zynq_gem: Use max-speed property from dt

Add support to use max-speed property from dt for
determining the supported speed. Use 1000Mbps as
default.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

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Merge tag 'xilinx-for-v2018.05' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2018.05

- Fix mkimage recognition
- Update all my fragments

ZynqMP:
- Use clk driver
- Support loading el

Merge tag 'xilinx-for-v2018.05' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2018.05

- Fix mkimage recognition
- Update all my fragments

ZynqMP:
- Use clk driver
- Support loading elfs in el1
- Various DTS and defconfig changes
- Enable newer pmufw versions
- Support more clocks
- Remove ep108
- Secure image support
- Fix memtest setup

Zynq:
- Enabling watchdog driver
- Support more clocks
- defconfig changes

fpga:
- Simplify error path

net:
- GMII case update

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net: zynq_gem: Dont run any phy detection logic for GMII case

This patch bypasses phy detection logic for GMII interface
and just depend on phy address received from DT. This patch
is required as ph

net: zynq_gem: Dont run any phy detection logic for GMII case

This patch bypasses phy detection logic for GMII interface
and just depend on phy address received from DT. This patch
is required as phy detection logic is different for some phys
like xilinx phy which can be connected over SGMII and GMII
interface.
This fixes the issue of ethernet failures when xilinx phy is
connected over GMII interface.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

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Merge git://git.denx.de/u-boot-spi