| 1a74e652 | 10-Jun-2022 |
Joel Stanley <joel@jms.id.au> |
phy: Only create NCSI PHY when it's present
phy_connect would unconditionally create a NCSI PHY device if the driver
was configured.
By detecting what the phy type is at runtime we can support NCSI
phy: Only create NCSI PHY when it's present
phy_connect would unconditionally create a NCSI PHY device if the driver
was configured.
By detecting what the phy type is at runtime we can support NCSI and
non-NCSI system with the same defconfig,
Link: https://lore.kernel.org/r/20220610080059.2333501-3-joel@jms.id.au
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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| 91c9cbab | 06-Nov-2018 |
Valentin-catalin Neacsu <valentin-catalin.neacsu@nxp.com> |
net: phy: aquantia: Print information on config
Print information about Aquantia system interface and firmware loaded
on the phy.
Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp
net: phy: aquantia: Print information on config
Print information about Aquantia system interface and firmware loaded
on the phy.
Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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| e57c9fdb | 16-Jan-2019 |
Carlo Caione <ccaione@baylibre.com> |
net: phy: realtek: Add functions to read PHY's extended registers
According to the datasheet to access the extended registers we have to:
1. Write Register 31 Data = 0x0XYZ (Page 0xXYZ)
2. Read/Wri
net: phy: realtek: Add functions to read PHY's extended registers
According to the datasheet to access the extended registers we have to:
1. Write Register 31 Data = 0x0XYZ (Page 0xXYZ)
2. Read/Write the target Register Data
3. Write Register 31 Data = 0x0000 or 0xa42 (switch back to IEEE
Standard Registers)
Hook the missing functions so that we can use the `mdio rx/wx` command to
easily access the extended registers.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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| 3b4cda34 | 29-Nov-2018 |
Andreas Pretzsch <apr@cn-eng.de> |
net: phy: micrel: fix KSZ9031 clock skew for values greater 0ps
For KSZ9021, all skew register fields are 4-bit wide.
For KSZ9031, the clock skew register fields are 5-bit wide.
The common code in
net: phy: micrel: fix KSZ9031 clock skew for values greater 0ps
For KSZ9021, all skew register fields are 4-bit wide.
For KSZ9031, the clock skew register fields are 5-bit wide.
The common code in ksz90x1_of_config_group calculating the combined
register value checks if the requested value is above the maximum
and uses this maximum if so. The calculation of this maximum uses
the register width, but the check itself does not. It uses a hardcoded
value of 0xf, which is too low in case of the 5-bit clock (0x1f).
This detail was probably lost during driver unification.
Effect (only for KSZ9031 clock skews): For values greater 900 (== 0ps),
this silently results in 1860 (== +960ps) instead of the requested one.
Fix the check by using the bit width instead of hardcoded value(s).
Signed-off-by: Andreas Pretzsch <apr@cn-eng.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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