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Revision tags: v00.04.15, v00.04.14, v00.04.13, v00.04.12, v00.04.11, v00.04.10, v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01, v00.04.00, v2021.04, v00.03.03, v2021.01, v2020.10, v2020.07, v00.02.13, v2020.04, v2020.01, v2019.10, v00.02.05, v00.02.04, v00.02.03, v00.02.02, v00.02.01, v2019.07, v00.02.00, v2019.04 |
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| #
d0423c44 |
| 16-Oct-2018 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-microblaze
Xilinx changes for v2018.11-rc2-v2
FPGA:
- Fix SPL fpga loading from FIT
ARM64:
- Fix gic accesses in EL2/EL1
Xilinx:
- Add dlc20 board support
- Add Ver
Merge git://git.denx.de/u-boot-microblaze
Xilinx changes for v2018.11-rc2-v2
FPGA:
- Fix SPL fpga loading from FIT
ARM64:
- Fix gic accesses in EL2/EL1
Xilinx:
- Add dlc20 board support
- Add Versal board support
- Sync defconfigs
- Enable MP via Kconfig
- Add missing efuse node
- Enable CDC for zcu100
cmd:
- Fix kgdb Kconfig dependency
show more ...
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| #
6bfe3fff |
| 13-Sep-2018 |
Michal Simek <michal.simek@xilinx.com> |
arm: zynq: Add support for DLC20 board
Xilinx DLC20 has I2C0 with EEPROM(1KB), UART1, GPIO, SD0 (EMMC 4GB),
USB0 device, ENET0, QSPI (16MB) and DDR(two of 256MB each).
Boards have mix of Winbond/ST
arm: zynq: Add support for DLC20 board
Xilinx DLC20 has I2C0 with EEPROM(1KB), UART1, GPIO, SD0 (EMMC 4GB),
USB0 device, ENET0, QSPI (16MB) and DDR(two of 256MB each).
Boards have mix of Winbond/ST QSPIs.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
show more ...
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