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Revision tags: v00.04.15, v00.04.14, v00.04.13, v00.04.12, v00.04.11, v00.04.10, v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01, v00.04.00, v2021.04, v00.03.03, v2021.01, v2020.10, v2020.07, v00.02.13, v2020.04, v2020.01, v2019.10, v00.02.05, v00.02.04, v00.02.03, v00.02.02, v00.02.01, v2019.07, v00.02.00, v2019.04, v2018.07, v2018.03, v2018.01, v2017.11 |
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| #
88e0d593 |
| 22-Nov-2016 |
Liviu Dudau <Liviu.Dudau@foss.arm.com> |
vexpress64: Juno: Change PCI buss addresses for IO to start from zero.
Juno uses a 1:1 mapping between CPU and PCI addresses for IO. First,
that will trip devices that cannot use more than 16 bits o
vexpress64: Juno: Change PCI buss addresses for IO to start from zero.
Juno uses a 1:1 mapping between CPU and PCI addresses for IO. First,
that will trip devices that cannot use more than 16 bits of addresses
for IO, second it is un-necessary as the system can handle zero-based
PCI addresses just fine.
Change the mapping to start IO bus addresses from zero.
Signed-off-by: Liviu Dudau <Liviu.Dudau@foss.arm.com>
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Revision tags: v2016.07, openbmc-20160624-1 |
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bc8d3bc0 |
| 18-Nov-2015 |
Ryan Harkin <ryan.harkin@linaro.org> |
vexpress64: compile Juno PCIe conditionally
Only compile in PCIe support if the board really uses it. Provide
a __weak stub for the init function if e.g. FVP is being built.
Signed-off-by: Ryan Har
vexpress64: compile Juno PCIe conditionally
Only compile in PCIe support if the board really uses it. Provide
a __weak stub for the init function if e.g. FVP is being built.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
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Revision tags: v2016.01-rc1 |
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| #
0ee1a22b |
| 13-Nov-2015 |
Andre Przywara <andre.przywara@arm.com> |
Juno: don't print PCI debug information by default
On a Juno r1 the PCI controller init routine outputs the rather boring
ATR entry information.
Do this only with DEBUG defined to avoid cluttering t
Juno: don't print PCI debug information by default
On a Juno r1 the PCI controller init routine outputs the rather boring
ATR entry information.
Do this only with DEBUG defined to avoid cluttering the user's
terminal.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Ryan Harkin <ryan.harkin@linaro.org>
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| #
a69fdc77 |
| 23-Oct-2015 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
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Revision tags: v2015.10 |
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| #
2fdc9b74 |
| 19-Oct-2015 |
Liviu Dudau <Liviu.Dudau@foss.arm.com> |
vexpress64: Juno: Add initialisation code for Juno R1 PCIe host bridge.
Juno R1 has an XpressRICH3 PCIe host bridge that needs to be initialised
in order for the Linux kernel to be able to enumerate
vexpress64: Juno: Add initialisation code for Juno R1 PCIe host bridge.
Juno R1 has an XpressRICH3 PCIe host bridge that needs to be initialised
in order for the Linux kernel to be able to enumerate the bus. Add
support code here that enables the host bridge, trains the links and
sets up the Address Translation Tables.
Signed-off-by: Liviu Dudau <Liviu.Dudau@foss.arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
[trini: Always declare vexpress64_pcie_init and continue handling logic
inside the function]
Signed-off-by: Tom Rini <trini@konsulko.com>
show more ...
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