0fd1359c | 17-Jan-2019 |
Andrew F. Davis <afd@ti.com> |
ARM: mach-omap2: Kconfig: Allow OMAP5 devices to set entry point
Like AM33xx and AM43xx, DRA7xx and AM57xx devices may need to have an non-standard boot address in memory. This may be due to the dev
ARM: mach-omap2: Kconfig: Allow OMAP5 devices to set entry point
Like AM33xx and AM43xx, DRA7xx and AM57xx devices may need to have an non-standard boot address in memory. This may be due to the device being a high security variant, which place the Initial SoftWare (ISW) after certificates and secure software.
Allow these devices to set this from Kconfig.
Signed-off-by: Andrew F. Davis <afd@ti.com>
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2b30b38b | 07-Dec-2018 |
Jean-Jacques Hiblot <jjhiblot@ti.com> |
omap: detect the board after DM is available
In order to use DM_I2C, we need to move the board detection after the early SPL initialization.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Rev
omap: detect the board after DM is available
In order to use DM_I2C, we need to move the board detection after the early SPL initialization.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
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94c6a89a | 12-Jun-2018 |
Nishanth Menon <nm@ti.com> |
ARM: mach-omap2: omap3/am335x: Enable ACR::IBE on Cortex-A8 SoCs for CVE-2017-5715
Enable CVE-2017-5715 option to set the IBE bit. This enables kernel workarounds necessary for the said CVE.
With t
ARM: mach-omap2: omap3/am335x: Enable ACR::IBE on Cortex-A8 SoCs for CVE-2017-5715
Enable CVE-2017-5715 option to set the IBE bit. This enables kernel workarounds necessary for the said CVE.
With this enabled, Linux reports: CPU0: Spectre v2: using BPIALL workaround
This workaround may need to be re-applied in OS environment around low power transition resume states where context of ACR would be lost (off-mode etc).
Signed-off-by: Nishanth Menon <nm@ti.com>
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