SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So

SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>

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Merge git://git.denx.de/u-boot-mmc

ARM: OMAP5: set mmc clock frequency to 192MHz

Now that omap_hsmmc has support for hs200 mode, change the clock
frequency to 192MHz. Also change the REFERENCE CLOCK frequency to
192MHz based on which

ARM: OMAP5: set mmc clock frequency to 192MHz

Now that omap_hsmmc has support for hs200 mode, change the clock
frequency to 192MHz. Also change the REFERENCE CLOCK frequency to
192MHz based on which the internal mmc clock divider is calculated.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>

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board: ti: dra76-evm: Add the pmic data

dra76-evm uses lp8736 and tps65917 pmic for powering on
various peripherals. Add data for these pmics and register
for dra76-evm.

Reviewed-by: Tom Rini <trin

board: ti: dra76-evm: Add the pmic data

dra76-evm uses lp8736 and tps65917 pmic for powering on
various peripherals. Add data for these pmics and register
for dra76-evm.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

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ARM: OMAP5: Enable support for AVS0 for OMAP5 production devices

OMAP5432 did go into production with AVS class0 registers which were
mutually exclusive from AVS Class 1.5 registers.

Most OMAP5-uEV

ARM: OMAP5: Enable support for AVS0 for OMAP5 production devices

OMAP5432 did go into production with AVS class0 registers which were
mutually exclusive from AVS Class 1.5 registers.

Most OMAP5-uEVM boards use the pre-production Class1.5 which has
production efuse registers set to 0. However on production devices,
these are set to valid data.

scale_vcore logic is already smart enough to detect this and use the
"Nominal voltage" on devices that do not have efuse registers populated.

On a test production device populated as follows:
MPU OPP_NOM:
=> md.l 0x04A0021C4 1
4a0021c4: 03a003e9 ....
(0x3e9 = 1.01v) vs nom voltage of 1.06v
MPU OPP_HIGH:
=> md.l 0x04A0021C8 1
4a0021c8: 03400485 ..@.

MM OPP_NOM:
=> md.l 0x04A0021A4 1
4a0021a4: 038003d4 ....
(0x3d4 = 980mV) vs nom voltage of 1.025v
MM OPP_OD:
=> md.l 0x04A0021A8 1
4a0021a8: 03600403 ..`.

CORE OPP_NOM:
=> md.l 0x04A0021D8 1
4a0021d8: 000003cf ....
(0x3cf = 975mV) vs nom voltage of 1.040v

Since the efuse values are'nt currently used, we do not regress on
existing pre-production samples (they continue to use nominal voltage).

But on boards that do have production samples populated, we can leverage
the optimal voltages necessary for proper operation.

Tested on:
a) 720-2644-001 OMAP5UEVM with production sample.
b) 750-2628-222(A) UEVM5432G-02 with pre-production sample.

Data based on OMAP5432 Technical reference Manual SWPU282AF (May
2012-Revised Aug 2016)

NOTE: All collaterals on OMAP5432 silicon itself seems to have been
removed from ti.com, though EVM details are still available:
http://www.ti.com/tool/OMAP5432-EVM

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

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ARM: OMAP5: Remove OPP_LOW Definitions for ES2.0

ES2.0 descopes OPP_LOW definition. So remove it from macros defined.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutl

ARM: OMAP5: Remove OPP_LOW Definitions for ES2.0

ES2.0 descopes OPP_LOW definition. So remove it from macros defined.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

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omap5: Migrate CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC to Kconfig

While in theory this value could be used in places outside of "omap5"
(such as OMAP4), we only make use of it today in OMAP5, so pl

omap5: Migrate CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC to Kconfig

While in theory this value could be used in places outside of "omap5"
(such as OMAP4), we only make use of it today in OMAP5, so place the
Kconfig entry there. Given that Kconfig lets us provide a default, we
drop CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC entirely. The contents of
doc/README.omap-reset-time make a good help entry, so adjust them
slightly and delete the file. Move the comment about range to where we
use the value now, and have Kconfig enforce the upper bound.

Signed-off-by: Tom Rini <trini@konsulko.com>

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board: ti: dra71x-evm: Add PMIC support

Add the pmic_data for LP873x PMIC which is used to power
up dra71x-evm.

Note: As per the DM[1] DRA71x supports only OP_NOM. So, updating
the efuse registers

board: ti: dra71x-evm: Add PMIC support

Add the pmic_data for LP873x PMIC which is used to power
up dra71x-evm.

Note: As per the DM[1] DRA71x supports only OP_NOM. So, updating
the efuse registers only to use OPP_NOM irrespective of any
CONFIG_DRA7_<VOLT>_OPP_{NOM,od,high} is defined.

[1] http://www.ti.com/product/DRA718/technicaldocuments

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

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ARM: DRA7: Redefine voltage and efuse macros per OPP using Kconfig

Redefine the macros used to define the voltage values and the
efuse register offsets based on OPP for all the voltage domains.
This

ARM: DRA7: Redefine voltage and efuse macros per OPP using Kconfig

Redefine the macros used to define the voltage values and the
efuse register offsets based on OPP for all the voltage domains.
This is done using Kconfig macros that can be set in a defconfig
or selected during a config step. This allows a voltage domain
to be configured/set to a corresponding voltage value depending
on the OPP selection choice.

The Kconfig choices have been added for MPU, DSPEVE, IVA and GPU
voltage domains, with the MPU domain restricted to OPP_NOM. The
OPP_OD and OPP_HIGH options will be added when the support for
configuring the MPU clock frequency is added. The clock
configuration for other voltage domains is out of scope in
u-boot code.

The CORE voltage domain does not have separate voltage values
and efuse register offset at different OPPs, while the MPU
voltage domain only has different efuse register offsets for
different OPPs, but uses the same voltage value. Any different
choices of OPPs for voltage domains on common ganged-rails
is automatically taken care to select the corresponding
highest OPP voltage value.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

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ARM: DRA7x/AM57xx: Get rid of CONFIG_AM57XX

CONFIG_AM57XX is just an unnecessary macro that is redundant given So,
remove the same instead of spreading through out the u-boot source
code and getting

ARM: DRA7x/AM57xx: Get rid of CONFIG_AM57XX

CONFIG_AM57XX is just an unnecessary macro that is redundant given So,
remove the same instead of spreading through out the u-boot source
code and getting in the way to maintain common code for DRA7x family.

Acked-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

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Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <sbabic@denx.de>

ARM: DRA7: Add macros for voltage values for all OPPs

Define specific macros for the voltage values for all voltage
domains for all applicable OPPs - OPP_NOM, OPP_OD and OPP_HIGH.
No separate macros

ARM: DRA7: Add macros for voltage values for all OPPs

Define specific macros for the voltage values for all voltage
domains for all applicable OPPs - OPP_NOM, OPP_OD and OPP_HIGH.
No separate macros are defined for VD_MPU and VD_CORE at OPP_OD
and OPP_HIGH as these use the same values as OPP_NOM.

The current macros will be used as common macros that can be
redefined appropriately based on a selected OPP configuration
at build time.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

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ARM: DRA7: Consolidate voltage macros across different SoCs

The voltage values for each voltage domain at an OPP is identical
across all the SoCs in the DRA7 family. The current code defines
one set

ARM: DRA7: Consolidate voltage macros across different SoCs

The voltage values for each voltage domain at an OPP is identical
across all the SoCs in the DRA7 family. The current code defines
one set of macros for DRA75x/DRA74x SoCs and another set for DRA72x
macros. Consolidate both these sets into a single set.

This is done so as to minimize the number of macros used when voltage
values will be added for other OPPs as well.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

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ARM: DRA7: Define common macros for efuse register offsets

Define a set of common macros for the efuse register offsets
(different for each OPP) that are used to get the AVS Class 0
voltage values a

ARM: DRA7: Define common macros for efuse register offsets

Define a set of common macros for the efuse register offsets
(different for each OPP) that are used to get the AVS Class 0
voltage values and ABB configuration values. Assign these
common macros to the register offsets for OPP_NOM by default
for all voltage domains. These common macros can then be
redefined properly to point to the OPP specific efuse register
offset based on the desired OPP to program a specific voltage
domain.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

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ARM: DRA7: Update/Correct MPU and CORE OPP_NOM voltage values

The current OPP_NOM voltage values defined for the MPU and CORE
voltage domains are based on the initial DRA75x_74x_SR1.1_DM data
manual

ARM: DRA7: Update/Correct MPU and CORE OPP_NOM voltage values

The current OPP_NOM voltage values defined for the MPU and CORE
voltage domains are based on the initial DRA75x_74x_SR1.1_DM data
manual. As per this DM, the PMIC boot voltage can be set to either
1.10V or 1.15V for VD_MPU, and either 1.06V or 1.15V for VD_CORE.
While the current values are correct, the latter set of values
are the values that are common across all DRA75x, DRA72x SoCs and
for all current Silicon revisions. So, update both the MPU and CORE
OPP_NOM voltages to 1.15V.

The macros are also slightly reorganized so that both the MPU and
CORE voltage domain values are defined together.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

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ARM: DRA7: Enable clocks for USB OTGSS2 and USB PHY2

Enabled clocks for the second dwc3 controller and second USB PHY present in
DRA7.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed

ARM: DRA7: Enable clocks for USB OTGSS2 and USB PHY2

Enabled clocks for the second dwc3 controller and second USB PHY present in
DRA7.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

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Merge remote-tracking branch 'u-boot/master' into 'u-boot-arm/master'

Merge branch 'master' of git://git.denx.de/u-boot

Merge branch 'master' of git://git.denx.de/u-boot-ti

ARM: OMAP5: DRA7xx: Add support for power rail grouping

On the DRA72x (J6Eco) EVM one PMIC SMPS is powering three SoC
core rails. This concept of using one SMPS to supply multiple
core domains (in v

ARM: OMAP5: DRA7xx: Add support for power rail grouping

On the DRA72x (J6Eco) EVM one PMIC SMPS is powering three SoC
core rails. This concept of using one SMPS to supply multiple
core domains (in various, although limited combinations, per
primary device use case) has now become common and is used by
many customer J6/J6Eco designs; it is supported by a number of
corresponding PMIC OTP versions.

This patch implements correct operation of the core voltages
scaling routine by ensuring that each SMPS that is supplying
more than one domain shall be written only once, and with the
highest voltage of those fused in the SoC (or of those defined
in the corresponding header if fuse read is disabled or fails)
for the power rails belonging to the group.

The patch also replaces some PMIC-related magic numbers with
the appropriate definitions. The default OPP_NOM voltages for
the DRA7xx SoCs are updated as well, per the latest DMs.

Signed-off-by: Lubomir Popov <l-popov@ti.com>

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Merge branch 'master' of git://git.denx.de/u-boot-ti

arm: omap: add support for am57xx devices

just add a few ifdefs around because this
device is very similar to dra7xxx.

Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>

arm: omap5: tps659038: rename regulator defines

Those regulators don't have any coupling with
what they supply, so remove the suffixes in order
to not confuse anybody.

Signed-off-by: Felipe Balbi <

arm: omap5: tps659038: rename regulator defines

Those regulators don't have any coupling with
what they supply, so remove the suffixes in order
to not confuse anybody.

Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>

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Merge branch 'master' of git://git.denx.de/u-boot-arm

Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'