Merge git://git.denx.de/u-boot-fsl-qoriq

- Support of NXP's LX2160RDB and LX2160QDS platform
- Enable SATA DM model for NXP's ARM SoCs

armv8: lx2160a: Update CONFIG_SYS_FSL_PEBUF_BASE

As per hardware documentation,
CONFIG_SYS_FSL_PEBUF_BASE for lx2160a is 0x1c00000000

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-b

armv8: lx2160a: Update CONFIG_SYS_FSL_PEBUF_BASE

As per hardware documentation,
CONFIG_SYS_FSL_PEBUF_BASE for lx2160a is 0x1c00000000

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

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Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriq

Add TFA boot flow for some Layerscape platforms
Add support for lx2160a SoC

[trini: Add a bunch of missing MAINTAINERS e

Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriq

Add TFA boot flow for some Layerscape platforms
Add support for lx2160a SoC

[trini: Add a bunch of missing MAINTAINERS entries]
Signed-off-by: Tom Rini <trini@konsulko.com>

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armv8:fsl-layerscape: Add support for Chassis 3.2

NXP layerscape architecture Chassis 3.2 builds upon chassis3
architecture with changes like DDR Memory map change,
removal of IFC and support of upt

armv8:fsl-layerscape: Add support for Chassis 3.2

NXP layerscape architecture Chassis 3.2 builds upon chassis3
architecture with changes like DDR Memory map change,
removal of IFC and support of upto 8 I2C controller.

Patch add README.lsch3_2 and the above changes under
macro CONFIG_NXP_LSCH3_2.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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move data structure out of cpu.h

Move static definitions to cpu.c file, as it doesn't allow
the cpu.h file to be included in multiple c files.

Signed-off-by: York Sun <york.sun@nxp.com>

SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So

SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>

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Merge git://git.denx.de/u-boot-fsl-qoriq

armv8: fsl: ifc: Put IFC related code under CONFIG_FSL_IFC

IFC code is put under CONFIG_FSL_IFC

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

Merge git://git.denx.de/u-boot-fsl-qoriq

armv8: ls1088a: Add NXP LS1088A SoC support

LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory contr

armv8: ls1088a: Add NXP LS1088A SoC support

LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8: fsl-layerscape: Fix final MMU table for QSPI and IFC

For QSPI and IFC addresses execution shouldn't be allowed
when u-boot running from DDR. Revise the MMU final table
to enforce execute-neve

armv8: fsl-layerscape: Fix final MMU table for QSPI and IFC

For QSPI and IFC addresses execution shouldn't be allowed
when u-boot running from DDR. Revise the MMU final table
to enforce execute-never bits.

Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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common: freescale: Move arch-specific declarations

The declarations should not be in common.h. Move them to the arch-specific
headers.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Fixup th

common: freescale: Move arch-specific declarations

The declarations should not be in common.h. Move them to the arch-specific
headers.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)]
Signed-off-by: Tom Rini <trini@konsulko.com>

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Merge git://git.denx.de/u-boot-fsl-qoriq

armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support

The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and
is built on layerscape architecture. It is 40-pin derivative of
LS2084A

armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support

The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and
is built on layerscape architecture. It is 40-pin derivative of
LS2084A (non-AIOP personality of LS2088A). So feature-wise it is
same as LS2084A. LS2041A is a 4-core personality of LS2081A.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <sbabic@denx.de>

Merge git://git.denx.de/u-boot-fsl-qoriq

armv8: ls2080a: Drop macro CONFIG_LS2080A

Use CONFIG_ARCH_LS2080A instead.

Signed-off-by: York Sun <york.sun@nxp.com>

Merge git://git.denx.de/u-boot-fsl-qoriq

armv8: layerscape: Update early MMU for DDR after initialization

In early MMU table, DDR has to be mapped as device memory to avoid
speculative access. After DDR is initialized, it needs to be updat

armv8: layerscape: Update early MMU for DDR after initialization

In early MMU table, DDR has to be mapped as device memory to avoid
speculative access. After DDR is initialized, it needs to be updated
to normal memory to allow code execution. To simplify the code,
dram_init() is moved into a common file as a weak function.

Signed-off-by: York Sun <york.sun@nxp.com>

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Merge git://git.denx.de/u-boot-fsl-qoriq

ARMv8/fsl-layerscape: Correct the OCRAM size

The real size of OCRAM is 128KiB, so correct the size of OCRAM.
And OCRAM reserved 2MiB space, then add a new macro to describe
it, which is used for MMU

ARMv8/fsl-layerscape: Correct the OCRAM size

The real size of OCRAM is 128KiB, so correct the size of OCRAM.
And OCRAM reserved 2MiB space, then add a new macro to describe
it, which is used for MMU setup.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <sbabic@denx.de>

Merge git://git.denx.de/u-boot-fsl-qoriq

Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
arch/arm/Kconfig

armv8: fsl-layerscape: Add NXP LS2088A SoC support

The QorIQ LS2088A SoC is built on layerscape architecture.

It is similar to LS2080A SoC with some differences like
1)Timer controller offset is di

armv8: fsl-layerscape: Add NXP LS2088A SoC support

The QorIQ LS2088A SoC is built on layerscape architecture.

It is similar to LS2080A SoC with some differences like
1)Timer controller offset is different
2)It has A72 cores
3)It supports TZASC module

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

show more ...

Merge git://git.denx.de/u-boot-fsl-qoriq