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Revision tags: v00.04.15, v00.04.14, v00.04.13, v00.04.12, v00.04.11, v00.04.10, v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01, v00.04.00, v2021.04, v00.03.03, v2021.01, v2020.10, v2020.07, v00.02.13, v2020.04, v2020.01, v2019.10, v00.02.05, v00.02.04, v00.02.03, v00.02.02, v00.02.01, v2019.07, v00.02.00, v2019.04 |
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| #
d391c13c |
| 15-Feb-2019 |
Tom Rini <trini@konsulko.com> |
Merge tag 'xilinx-for-v2019.04-rc2' of git://git.denx.de/u-boot-microblaze
Xilinx changes for v2019.04-rc2
xilinx:
- Start to use distro boot commands first
- Setup fdtfile on ZynqMP
- Move mac add
Merge tag 'xilinx-for-v2019.04-rc2' of git://git.denx.de/u-boot-microblaze
Xilinx changes for v2019.04-rc2
xilinx:
- Start to use distro boot commands first
- Setup fdtfile on ZynqMP
- Move mac addr eeprom read to common location
- Convert to OF_SEPARATE
- Switch all board to DM_I2C
- Some DT syncs
i2c:
- Remove !DM_I2C zynq driver
versal:
- Enable some more features
- Add mini configurations
show more ...
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| #
053d4bd4 |
| 14-Nov-2018 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
arm64: zynqmp: Change the spi-rx-bus-width property to x1
As per the zc1275 design x1 mode is enabled so changing the
spi-rx-bus-width property to x1.
Signed-off-by: Venkatesh Yadav Abbarapu <venka
arm64: zynqmp: Change the spi-rx-bus-width property to x1
As per the zc1275 design x1 mode is enabled so changing the
spi-rx-bus-width property to x1.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
show more ...
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| #
0a3d59e0 |
| 03-Dec-2018 |
Tom Rini <trini@konsulko.com> |
Merge tag 'xilinx-for-v2019.01' of git://git.denx.de/u-boot-microblaze
Xilinx changes for v2019.01
microblaze:
- Use default functions for memory decoding
- Showing model from DT
zynq:
- Fix spi f
Merge tag 'xilinx-for-v2019.01' of git://git.denx.de/u-boot-microblaze
Xilinx changes for v2019.01
microblaze:
- Use default functions for memory decoding
- Showing model from DT
zynq:
- Fix spi flash DTs
- Fix zynq_help_text with CONFIG_SYS_LONGHELP
- Tune cse/mini configurations
- Enabling cse/mini testing with current targets
zynqmp:
- Enable gzip SPL support
- Fix chip detection logic
- Tune mini configurations
- DT fixes(spi-flash, models, clocks, etc)
- Add support for OF_SEPARATE configurations
- Enabling mini testing with current targets
- Add mini mtest configuration
- Some minor config setting
nand:
- arasan: Add subpage configuration
net:
- gem: Add 64bit DMA support
show more ...
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| #
0ed45f00 |
| 26-Jul-2018 |
Michal Simek <michal.simek@xilinx.com> |
arm64: zynqmp: Wire spi-flash compatible string with flashes
Enable reading tx and rx buswidth from DT via spi-uclass.
To get these from uclass spi-flash compatible string has to be added
to flash n
arm64: zynqmp: Wire spi-flash compatible string with flashes
Enable reading tx and rx buswidth from DT via spi-uclass.
To get these from uclass spi-flash compatible string has to be added
to flash node.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
show more ...
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Revision tags: v2018.07 |
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| #
3b52847a |
| 11-May-2018 |
Tom Rini <trini@konsulko.com> |
Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze
Xilinx changes for v2018.07
microblaze:
- Align defconfig
zynq:
- Rework fpga initialization and cpuinfo handling
zynqmp
Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze
Xilinx changes for v2018.07
microblaze:
- Align defconfig
zynq:
- Rework fpga initialization and cpuinfo handling
zynqmp:
- Add ZynqMP R5 support
- Wire and enable watchdog on zcu100-revC
- Setup MMU map for DDR at run time
- Show board info based on DT and cleanup IDENT_STRING
zynqmp tools:
- Add read partition support
- Add initial support for Xilinx bif format for boot.bin generation
mmc:
- Fix get_timer usage on 64bit cpus
- Add support for SD3.0 UHS mode
nand-zynq:
- Add support for 16bit buswidth
- Use address cycles from onfi params
scsi:
- convert ceva sata to UCLASS_AHCI
timer:
- Add Cadence TTC for ZynqMP r5
watchdog:
- Minor cadence driver cleanup
show more ...
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| #
04ab29ab |
| 11-Apr-2018 |
Siva Durga Prasad Paladugu <sivadur@xilinx.com> |
arm64: zynqmp: Add new defconfig for zc1275 revB
This patch enables support zc1275 revB board. It has
SD added compared to revA. The same configuration will
work for RevC boards aswell.
Signed-off-
arm64: zynqmp: Add new defconfig for zc1275 revB
This patch enables support zc1275 revB board. It has
SD added compared to revA. The same configuration will
work for RevC boards aswell.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
show more ...
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