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Revision tags: v00.04.15 |
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b4919f04 |
| 26-Jun-2023 |
Kevin-Chen, Chen <kevin_chen@aspeedtech.com> |
Merge branch pull request #16 into aspeed-dev-v2019.04.
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Revision tags: v00.04.14, v00.04.13, v00.04.12 |
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84661b4d |
| 07-Jul-2022 |
Jae Hyun Yoo <quic_jaehyoo@quicinc.com> |
ARM: dts: ast2600-qcom-dc-scm-v1: enable HACE
Enable HACE to support SPL boot.
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Link: https://lore.kernel.org/r/20220707223058.2722999-2-quic_j
ARM: dts: ast2600-qcom-dc-scm-v1: enable HACE
Enable HACE to support SPL boot.
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Link: https://lore.kernel.org/r/20220707223058.2722999-2-quic_jaehyoo@quicinc.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Revision tags: v00.04.11 |
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2b13d886 |
| 08-Jun-2022 |
Graeme Gregory <quic_ggregory@quicinc.com> |
ARM: dts: aspeed: add Qualcomm DC-SCM V1
Add initial version of device tree for Qualcomm DC-SCM V1 BMC which is
equipped with Aspeed AST2600 BMC SoC.
Signed-off-by: Graeme Gregory <quic_ggregory@qu
ARM: dts: aspeed: add Qualcomm DC-SCM V1
Add initial version of device tree for Qualcomm DC-SCM V1 BMC which is
equipped with Aspeed AST2600 BMC SoC.
Signed-off-by: Graeme Gregory <quic_ggregory@quicinc.com>
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Link: https://lore.kernel.org/r/20220608204351.1310956-1-quic_jaehyoo@quicinc.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
show more ...
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