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Revision tags: v00.04.15, v00.04.14, v00.04.13, v00.04.12 |
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95877f46 |
| 27-Jul-2022 |
Chia-Wei Wang <chiawei_wang@aspeedtech.com> |
Merge branch pull request #14 into aspeed-dev-v2019.04
Change-Id: Ib8e72966367a58286d91adc0378072e0591ab571
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Revision tags: v00.04.11 |
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bddbeb1a |
| 08-Jun-2022 |
Cédric Le Goater <clg@kaod.org> |
ARM: dts: aspeed: Remove "spi-flash" compatible
The underlying SoC definitions use compatible "jedec,spi-nor", so does
the aspeed SPI driver, this to be in sync with Linux and the latest
U-Boot.
Si
ARM: dts: aspeed: Remove "spi-flash" compatible
The underlying SoC definitions use compatible "jedec,spi-nor", so does
the aspeed SPI driver, this to be in sync with Linux and the latest
U-Boot.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20220608061455.365123-2-clg@kaod.org
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Revision tags: v00.04.10, v00.04.09, v00.04.08 |
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774a3174 |
| 17-Jan-2022 |
Ryan Chen <ryan_chen@aspeedtech.com> |
remove pcie rc enable
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Change-Id: I89d13fc4edb17074d62d5a85f50bea103e1121b4
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Revision tags: v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03 |
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4f7bd3b2 |
| 29-Jul-2021 |
Chia-Wei Wang <chiawei_wang@aspeedtech.com> |
aspeed: cosmetic: Rename ARCY to ACRY
v2: Fix typo in defconfigs
v1: Fix the typo of ARCY to ACRY.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: Ieeada4ff502fa6d327831a4b7e
aspeed: cosmetic: Rename ARCY to ACRY
v2: Fix typo in defconfigs
v1: Fix the typo of ARCY to ACRY.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: Ieeada4ff502fa6d327831a4b7e4dd5001c1f26c3
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Revision tags: v00.04.02, v00.04.01 |
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32d698c9 |
| 02-Jul-2021 |
Chia-Wei Wang <chiawei_wang@aspeedtech.com> |
arm/dts: ast2600-intel: Enable HACE and ARCY
Enable HACE/ARCY ASPEED HW crypto engines.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: Ia231d09b3983b3b24a315358defc4bff162ee9
arm/dts: ast2600-intel: Enable HACE and ARCY
Enable HACE/ARCY ASPEED HW crypto engines.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: Ia231d09b3983b3b24a315358defc4bff162ee93d
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Revision tags: v00.04.00, v2021.04 |
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fabbeb33 |
| 09-Mar-2021 |
Chia-Wei, Wang <chiawei_wang@aspeedtech.com> |
board: ast2600-intel: Add Intel EGS CRB support
Add support for Intel EGS CRB, where AST2600 is
embedded as the BMC.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Change-Id: I66717537
board: ast2600-intel: Add Intel EGS CRB support
Add support for Intel EGS CRB, where AST2600 is
embedded as the BMC.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Change-Id: I6671753779927ce42b8890f94458f033cecacd40
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